MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 249

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.5.5.5
The real time counter event register (RTEVR), shown in
interrupts. The register can be read at any time.
RTEVR bits are cleared by writing ones. Writing zeros does not affect the value of the status bits.
Table 5-44
5.5.5.6
The real time counter alarm register (RTALR), shown in
value. When the value of the RTC counter equals the RTALR[ALRM] value, a maskable interrupt is
generated.
Table 5-45
Freescale Semiconductor
Offset 0x10
0–29
0–31
Reset
Bits
Bits
Offset 0x14
Reset 1
30
31
W
R
W
R
0
Name
0
Name
ALRM RTC alarm value.
AIF
SIF
—
defines the bit fields of RTEVR.
defines the bit fields of RTALR.
1
Real Time Counter Event Register (RTEVR)
Real Time Counter Alarm Register (RTALR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
Write reserved, read = 0
Alarm interrupt flag bit.
Used to indicate the alarm interrupt. It is set if the RTC issues an interrupt after the RTC counter counts to
zero.
Second interrupt flag bit.
Used to indicate the every-second interrupt. This status bit is set each time that the prescaler count reaches
zero and should be cleared by software.
The alarm interrupt is generated when the value of the RTC counter equals RTALR[ALRM].
1
1
1
Figure 5-29. Real Time Counter Event Register (RTEVR)
Figure 5-30. Real Time Counter Alarm Register (RTALR)
1
1
1
1
Table 5-44. RTEVR Bit Settings
Table 5-45. RTALR Bit Settings
1
1
1
1
—
1
All zeros
ALRM
1
Description
Description
Figure
Figure
1
1
1
5-29, is used to report the source of the
5-30, contains the 32-bit alarm (ALRM)
1
1
1
1
1
1
1
1
System Configuration
Access: Read/Write
1
1
Access: w1c
29
1
w1c w1c
AIF SIF
30
1
5-41
31
31
1