MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 540

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.5.2.3
Principally, a read-modify-write cycle is a read cycle immediately followed by a write cycle. Because the
write cycle will have a new address phase in any case, this basically is the same case as an address phase
after a previous read.
10.5.2.4
The flexibility of the UPM allows the user to insert additional address phases during read cycles by
changing the AMX field, therefore turning around the bus during one pattern. The eLBC automatically
inserts a single bus turnaround cycle if the bus (LAD) was previously high impedance for any reason, such
as a read, before LALE is driven and LAD is driven with the new address. The turnaround cycle is not
inserted on a write, because the bus was already driven to begin with.
However, bus contention could potentially still occur on the far side of a bus transceiver. It is the
responsibility of the designer of the UPM pattern to guarantee that enough idle cycles are inserted in the
UPM pattern to avoid this.
10.5.3
The eLBC supports 8- and 16-bit data port sizes. However, the bus requires that the portion of the data bus
used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on LAD[0:15], and
an 8-bit port must reside on LAD[0:7]. The local bus always tries to transfer the maximum amount of data
on all bus cycles.
10-92
0
OP0
OP0
OP2
OP4
OP6
OP0
OP7
Interface to Different Port-Size Devices
LAD[0:7]
Read-Modify-Write Cycle for Parity Protected Memory Banks
UPM Cycles with Additional Address Phases
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 10-74
8-Bit Port Size
OP1
OP1
OP3
OP5
OP7
LAD[8:15]
Figure 10-74. Interface to Different Port-Size Devices
16-Bit Port Size
shows the device connections on the data bus.
OP2
OP3
31
OP4
OP5
Interface Output Register
OP6
Freescale Semiconductor
OP7
63