MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 650

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14.1.4.2
All execution units (EUs) are memory-mapped, and can be used entirely through register read/write
access. The SEC operates as a slave, and the host must write the information typically provided through
the descriptor into the appropriate registers and FIFOs of the SEC. This method is more CPU intensive,
and requires a great deal of familiarity with SEC registers. It is recommended that host-controlled access
be used only for operations using a single EU, and for debug purposes.
For more information, refer to
14.2
Table 14-2
in the execution units. The 18-bit SEC address bus value is shown. These address values are offsets from
IMMRBAR. See
for more information.
Note that these tables show addresses of 64-bit words; the three least-significant address bits that are used
to select bytes within 64-bit words are not shown.
Table 14-3
14-8
0x3_0000–0x3_0FFF
0x3_2000–0x3_2FFF
0x3_4000–0x3_4FFF
0x3_6000–0x3_6FFF
0x3_1000–0x3_10FF Controller Arbiter/controller control register space
0x3_1100–0x3_11FF
Address Offset
Address Offset
(AD 17–0)
(AD 17–0)
0x3_1008
0x3_1010
0x3_1018
0x3_1020
Configuration of Internal Memory Space
shows the base address map, while
shows the system address map showing all functional registers.
Host-Controlled Access
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 5.2.4.1, “Internal Memory Map Registers Base Address Register (IMMRBAR),”
IMR—Interrupt mask register
ISR—Interrupt status register
ICR—Interrupt clear register
ID—Identification register
Channel
Module
MDEU
AESU
DEU
—
DES/3DES execution unit
Reserved
Channel
AES execution unit
Message digest execution unit
Section 14.6, “Controller.”
Table 14-2. SEC Address Map
Table 14-3. SEC Address Map
Register
Description
Table 14-3
Controller
provides the address map, including all registers
Resource
control
Data control
EU
Type
—
Access
R/W
W
R
R
Section 14.6, “Controller”
Section 14.5, “Channel”
Section 14.4.1, “Data Encryption
Standard Execution Unit (DEU)”
Section 14.4.3, “Advanced
Encryption Standard Execution
Unit (AESU)”
Section 14.4.2, “Message Digest
Execution Unit (MDEU)”
Access
By
Freescale Semiconductor
Reference
—
14.6.4.2/14-68
14.6.4.3/14-70
14.6.4.4/14-71
14.6.4.5/14-73
Section/Page