MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 605

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

outbound window, or where an outbound translation window points back into an inbound window, are not
allowed.
Table 13-18
13.3.2.12 PCI Inbound Base Address Registers (PIBAR n )
PIBARn contains fields for defining the starting point of the inbound windows in the PCI memory space.
A write to a PIBARn register also causes a change in the base address bits in the corresponding GPL base
address register in the PCI configuration space.
Table 13-19
Freescale Semiconductor
Offset 0x38 (n=2)
Offset 0x40 (n=2)
Reset
Reset
12–31
0–31
0–11
Bits
Bits
W
W
R
R
0x50 (n=1)
0x68 (n=0)
0x58 (n=1)
0x70 (n=0)
0
0
shows the bit settings of PITARn.
shows the bit settings of PIBARn.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
Name
BA
TA
—
Figure 13-15. PCI Inbound Translation Address Registers (PITAR n )
Base address. Contains the starting address in the PCI memory space of the inbound window. This
field corresponds to bits 43–12 of a 64-bit address. In PIBAR0, the upper 12 bits are reserved
because only a 32-bit address is supported. The specified address must be aligned to the window
size, as defined by PIWAR n [IWS].
Reserved
Translation address. Contains the starting address of the inbound translated address. TA
corresponds to the 20 highest-order bits of a 32-bit local address. The specified address must be
aligned to the window size, as defined by PIWAR n [IWS].
Figure 13-16. PCI Inbound Base Address Registers (PIBAR n )
—
Table 13-19. PIBAR n Field Descriptions
Table 13-18. PITAR n Field Descriptions
11 12
Figure 13-16
All zeros
All zeros
BA
Description
Description
shows the PIBARx fields.
TA
Access: Read/Write
Access: Read/Write
PCI Bus Interface
13-23
31
31