MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 562

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DMA/Messaging Unit
12.2
Table 12-1
12-2
0x0_805C
0x0_81A0
0x0_81A4
0x0_8030
0x0_8034
0x0_8050
0x0_8054
0x0_8058
0x0_8060
0x0_8068
0x0_8080
0x0_8084
0x0_8100
0x0_8104
0x0_8108
0x0_8110
0x0_8118
0x0_8120
0x0_8124
0x0_8180
0x0_8184
0x0_8188
0x0_8190
0x0_8198
0x0_8200
0x0_8204
0x0_8208
0x0_8210
Offset
— Data chaining and direct mode
— Interrupt on completed segment, chain, and error
Memory Map/Register Definition
lists the address and access of the memory map module.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
OMISR—Outbound message interrupt status register
OMIMR—Outbound message interrupt mask register
IMR0—Inbound message register 0
IMR1—Inbound message register 1
OMR0—Outbound message register 0
OMR1—Outbound message register 1
ODR—Outbound doorbell register
IDR—Inbound doorbell register
IMISR—Inbound message interrupt status register
IMIMR—Inbound message interrupt mask register
DMAMR0—DMA 0 mode register
DMASR0—DMA 0 status register
DMACDAR0—DMA 0 current descriptor address register
DMASAR0—DMA 0 source address register
DMADAR0—DMA 0 destination address register
DMABCR0—DMA 0 byte count register
DMANDAR0—DMA 0 next descriptor address register
DMAMR1—DMA 1 mode register
DMASR1—DMA 1 status register
DMACDAR1—DMA 1 current descriptor address register
DMASAR1—DMA 1 source address register
DMADAR1—DMA 1 destination address register
DMABCR1—DMA 1 byte count register
DMANDAR1—DMA 1 next descriptor address register
DMAMR2—DMA 2 mode register
DMASR2—DMA 2 status register
DMACDAR2—DMA 2 current descriptor address register
DMASAR2—DMA 2 source address register
Register
Table 12-1. Module Memory Map
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
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