MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1141

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x020
19.4.1
19.4.1.1
SPMODE, shown in
Reset
Table 19-4
Freescale Semiconductor
0x038–0xFFF
0x000–0x01F
Bits
W
0
1
2
3
R
Offset
0x02C
0x020
0x024
0x028
0x030
0x034
— LOOP CI CP DIV16 REV M/S EN
0
Name
LOOP Loop mode. Enables local loopback operation.
CP
—
CI
1
describes the SPMODE fields.
Register Descriptions
SPI Mode Register (SPMODE)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
Reserved. Should be cleared.
0 Normal operation.
1 Loopback mode. Used to test the SPI controller internal functionality, the transmitter output is internally
The SPI acts normally in loop back mode; therefore, negating SPISEL in slave mode stops transmission,
negating it in master mode and causing and MME error.
Clock invert. Inverts SPI clock polarity. See
0 The inactive state of SPICLK is low.
1 The inactive state of SPICLK is high.
Clock phase. Selects the transfer format. See
0 SPICLK starts toggling at the middle of the data transfer.
1 SPICLK starts toggling at the beginning of the data transfer.
Reserved
SPI mode register (SPMODE)
SPI event register (SPIE)
SPI mask register (SPIM)
SPI command register (SPCOM)
SPI transmit register (SPITD)
SPI receive register (SPIRD)
Reserved
connected to the receiver input. The receiver and transmitter operate normally, except that received data
is ignored.
3
Figure
4
Figure 19-4. SPMODE-SPI Mode Register Definition
19-4, controls both the SPI operation mode and clock source.
5
6
Table 19-4. SPMODE Field Descriptions
Register
Table 19-3. SPI Register Summary
7
8
LEN
11 12
Figure 19-5
All zeros
PM
Figure 19-5
Description
15 16
Access
and
Mixed
R/W
R/W
—
and
—
W
W
—
R
Figure 19-6
18 19
Figure 19-6
OD
0xFFFF_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
20
Reset Value
for more information
—
—
for more information.
Serial Peripheral Interface
—
19.4.1.2/1919-12
19.4.1.3/1919-13
19.4.1.4/1919-14
19.4.1.5/1919-14
19.4.1.6/1919-15
19.4.1.1/1919-9
Access: Read/write
Section/Page
—
—
19-9
31