MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 927

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half Duplex mode.
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
Set up the MII Mgmt for a write cycle to TBI’s AN Advertisement register (write the PHY address and Register address),
This enables the TBI to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
Set up the MII Mgmt for a write cycle to TBI’s Control register (write the PHY address and Register address),
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx’d)
The PHY Status control register is at address 0x1 and in this case the PHY Address is 0x10.
Writing to MII Mgmt Control with 16-bit data intended for TBI’s AN Advertisement register,
(Uses the PHY address (0x10) and Register address (6) placed in MIIMADD register),
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),
The AN Advertisement register is at offset address 0x04 from the TBI’s address.
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Table 15-178. SGMII Mode Register Initialization Steps (continued)
Writing to MII Mgmt Control with 16-bit data intended for TBI’s Control register,
the control register (CR) is at offset address 0x00 from the TBI’s address.
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0110]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]
MIIMCON[0000_0000_0000_0000_0001_0011_0100_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0100]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0001]
Perform an MII Mgmt read cycle of AN Expansion Register.
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
read the MIIMSTAT register and check bit 10 (AN Done)
Check to see if PHY has completed Auto-Negotiation.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Perform an MII Mgmt write cycle to TBI.
Perform an MII Mgmt write cycle to TBI.
Additional SerDes setup as required
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
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15-209