MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 381

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 8-21
SERFR.
Table 8-22
8.5.14
Each implemented bit in SERMR, shown in
source (MCP). The user masks an MCP by clearing and enables an interrupt by setting the corresponding
SERMR bit. When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of
the corresponding SERMR bit although no MCP request is passed to the core in this case. The SERMR
can be read by the user at any time.
Freescale Semiconductor
0–31 INT n Each implemented bit in the SERSR, listed in
Bits Name
lists the implemented SERSR bits. Note that these field assignments are valid for SERMR and
defines the bit fields of SERSR.
System Error Mask Register (SERMR)
(mcp). When an error interrupt signal is received, the interrupt controller sets the corresponding SERSR bit.
SERSR bits are cleared by writing ones to them. Unmasked event register bits should be cleared before clearing
SERSR bits. Because the user can only clear bits in this register, writing zeros to this register has no effect.
SERSR bits are cleared by power-on reset. Subsequent soft and hard resets do not affect SERSR bit states.
For unimplemented bits (listed as reserved in
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 8-21. SERSR/SERMR/SERFR Bit Assignments
1
Table 8-22. SERSR Field Descriptions
This bit is valid only if the IRQ0 signal is
configured as an external MCP interrupt
(SEMSR[SIRQ0] = 1)
16–31
8–14
Bits
15
0
1
2
3
4
5
6
7
Figure
Table
Table
8-17, corresponds to an external and an internal mcp
Description
8-21, corresponds to an external and an internal error source
8-21), writes are ignored, read = 0
IRQ0
Field
WDT
SBA
MU
PCI
—
—
—
—
—
—
1
Integrated Programmable Interrupt Controller (IPIC)
8-23