MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 685

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.3.3
The AESU data size register (AESUDSR), shown in
message block. Acceptable sizes vary depending on the AES mode selected. In ECB, CBC, and CTR
mode, the message processed by the AESU must be a multiple of 128 bits; the AESU does not
automatically pad messages out to 128-bit blocks. In CCM mode, data size must be a multiple of 8 bits.
In XOR mode the data size must be a multiple of 256 bits (32 bytes). If an improper data size is written, a
data size error is generated. Only the lowest 3, 7, or 8 bits of the data size register are checked to determine
if there is a data size error. Since all upper bits are ignored, the entire message length (in bits) can be written
to this register.
The AESUDSR is cleared when the AESU is reset or re-initialized.
Writing to the AESUDSR signals the AESU to start processing data from the shared symmetric input FIFO
as soon as it is available. If the value of data size is modified during processing, a context error is
generated.
14.4.3.4
The AESU reset control register (AESURCR), shown in
AESU, as defined by the three self-clearing bits.
Freescale Semiconductor
Reset
Reset
Reset
Field
Field
Field
Addr
Addr
Addr
R/W
R/W
R/W
AESU Data Size Register (AESUDSR)
AESU Reset Control Register (AESURCR)
0
0
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 14-29. AESU Reset Control Register (AESURCR)
Figure 14-28. AESU Data Size Register (AESUDSR)
Figure 14-27. AESU Key Size Register (AESUKSR)
—
—
—
AESU 0x3_4008
AESU 0x3_4010
AESU 0x3_4018
Figure
R/W
R/W
R/W
0
0
0
Figure
14-28, stores the number of bits in the final
14-29, allows three levels reset of just
51
51
52
52
Key Size (bytes)
Data Size (bits)
60
Security Engine (SEC) 2.2
RI
61
MI
62
SR
63
63
63
14-43