MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 788

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.3
The IPGIFG register is written by the user.
Table 15-42
15-70
Offset eTSEC1:0x2_4508; eTSEC2:0x2_5508
Reset 0
Bits
Bits
1–7
28
29
30
31
0
8
W
R
—
0
Inter-Packet-Gap, Part 1
Inter-Packet-Gap, Part 1
PAD/CRC
1
1
CRC EN
Non-Back-to-Back
Duplex
MPEN
Name
Non-Back-to-Back
describes the fields of the IPGIFG register.
Full
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)
Name
0
—
—
0
Magic packet enable for Ethernet modes. This bit is cleared by default. MPEN should be enabled only
after GRACEFUL RECEIVE STOP and GRACEFUL TRANSMIT STOP are completed successfully (in
other words, transmission and reception have stopped).
0 Normal receive behavior on receive, or Magic Packet mode has exited with reception of a valid
1 Commence Magic Packet detection by the MAC provided that frame reception is enabled in
Pad and append CRC. This bit is cleared by default.This bit must be set when in half-duplex mode
(MACCFG2[Full Duplex] is cleared).
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of
CRC enable. If the configuration bit PAD/CRC ENABLE or the per-packet PAD/CRC ENABLE is set,
CRC ENABLE is ignored. This bit is cleared by default.
0 Frames presented to the MAC have a valid length and contain a valid CRC.
1 The MAC appends a CRC on all frames. Clear this bit if frames presented to the MAC have a valid
Full duplex configure. This bit is cleared by default.
0 The MAC operates in half-duplex mode only.
1 The MAC operates in full-duplex mode.
0
Magic Packet.
MACCFG1. In this mode the MAC ignores all received frames until the specific Magic Packet frame
is received, at which point this bit is cleared by the eTSEC, and a maskable interrupt through
IEVENT[MAG] occurs.
padding requirement.
length and contain a valid CRC.
0
Table 15-41. MACCFG2 Field Descriptions (continued)
0
7
Reserved
This is a programmable field representing the optional carrier sense window referenced in
IEEE 802.3/4.2.3.2.1 ‘carrier deference’. If carrier is detected during the timing of IPGR1,
the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC
continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which
follows the two-thirds/one-third guideline.
Reserved
—
0
8
Figure 15-38. IPGIFG Register Definition
Table 15-42. IPGIFG Field Descriptions
Inter-Packet-Gap, Part 2
1
9
Non-Back-to-Back
1
0
Figure 15-38
0
0
0
15 16
0
0
describes the definition for IPGIFG.
Description
1
Minimum IFG
Description
Enforcement
0
1
0
0
0
23 24 25
0
—
0
Freescale Semiconductor
1
Inter-Packet-Gap
1
Access: Read/Write
Back-to-Back
0
0
0
0
31
0