MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 265

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 5-58
Freescale Semiconductor
Bits
0
1
2
3
4
5
6
7
Name
PCAS
SCAS
RST4
RST3
STP4
STP3
GM4
GM3
defines the bit fields of GTCFR2.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Pair-cascade mode
0 Normal operation.
1 Timers 3 and 4 cascade to form a 32-bit timer.
Note: This bit is ignored in super-cascade mode (GTCFR2[SCAS] = 1).
Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
Super cascade mode
0 Normal operation
1 Timers 1, 2, 3 and 4 cascade to form a 64-bit timer.
Note: In super-cascade mode (GTCFR2[SCAS] = 1) the pair-cascade mode bits are ignored,
Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
Stop timer 4
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 4, except the
Reset timer 4
0 Reset the timer 4, including GTMDR4, GTRFR4, GTCNR4, GTCPR4, and GTEVR4 (a software reset is
1 Enable the corresponding timer if the STP4 bit is cleared.
Gate mode for TGATE4
0 Restart gate mode. The TGATE4 is used to enable/disable count. A low level of TGATE4 enables and a
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE4 does not restart the
Gate mode for TGATE3
0 Restart gate mode. The TGATE3 is used to enable/disable count. A low level of TGATE3 enables and a
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE3 does not restart the
Note: In backward compatible mode (GTCFR1[BCM] = 0) this bit is ignored. The GTCFR2[GM4] bit
Stop timer 3
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 3, except the
Reset timer 3
0 Reset the timer 3, including GTMDR3, GTRFR3, GTCNR3, GTCPR3, and GTEVR3 (a software reset is
1 Enable the corresponding timer if the STP3 bit is cleared.
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
identical to an external reset).
falling edge of TGATE4 restarts the count (reset the dynamic counter’s count value to 0) and a high level
of TGATE4 disables the count.
appropriate count value in GTCNR4[CNV4].
falling edge of TGATE3 restarts the count (reset the dynamic counter’s count value to 0) and a high level
of TGATE3 disables the count.
appropriate count value in GTCNR3[CNV3].
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
identical to an external reset).
Thus, the user should first clear the RST3 and RST4 bits (without changing PCAS) and then, in a
separate write to the register, change the value of PCAS.
(GTCFR1/2[PCAS] = Don’t Care).
Thus, the user should first clear the RST1, RST2, RST3, and RST4 bits (without changing SCAS)
and then, in a separate write to the register, change the value of SCAS.
controls the gate mode for timers 3 and 4.
Table 5-58. GTCFR2 Bit Settings
Description
System Configuration
5-57