MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 408

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9.4.1.5
DDR SDRAM timing configuration register 1, shown in
between various SDRAM control commands.
Table 9-10
9-14
Offset 0x108
Reset
16–19
20–23
24–27
28–31
Bits
Bits
0
W
R
— PRETOACT
0
ODT_PD_EXIT ODT powerdown exit timing (t
Name
1
MRS_CYC
—
describes TIMING_CFG_1 fields.
Name
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
Reserved, should be cleared.
3
Figure 9-6. DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
4
ACTTOPRE
Reserved, should be cleared.
before ODT may be asserted.
0000 0 clock
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Reserved, should be cleared.
Mode register set cycle time (t
Register Set command until any other command.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Table 9-9. TIMING_CFG_0 Field Descriptions (continued)
Table 9-10. TIMING_CFG_1 Field Descriptions
7
— ACTTORW
8
9
11 12
AXPD
MRD
CASLAT
). Specifies how many clocks must pass after exiting powerdown
). Specifies the number of cycles that must pass after a Mode
All zeros
15 16
Description
Figure
Description
REFREC
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
1000–1111Reserved
9-6, sets the number of clock cycles
19 20 21
— WRREC — ACTTOACT — WRTORD
23 24 25
Freescale Semiconductor
Access: Read/Write
27 28 29
31