MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 174

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
Figure 4-1
4.2.3
The HRESET signal is initiated externally by asserting HRESET or internally when the device detects a
reason to generate an internal hard reset sequence. In both cases, the device continues asserting HRESET
throughout the HRESET state. The hard reset sequence time varies according to the configuration source
and SYS_CLK_IN (PCI host mode) or PCI_CLK (PCI agent mode) frequency. The reset configuration
input signals (CFG_RESET_SOURCE and CFG_CLKIN_DIV) are not sampled by hard reset (only by
power-on reset), so the device immediately starts loading the reset configuration words and configures the
device as explained in
sequence completes, the device releasesthe HRESET and signal and exits the HRESET state. An external
pull-up resistor should negate the signals. After negation is detected, a 16-cycle period is taken before
testing for the presence of an external (hard) reset.
4-8
PCI_CLK/PCI_SYNC_IN
CLKIN (Host Mode) or
Reset Configuration
Reset Configuration
Words Loading
Input Signals
shows a timing diagram of the power-on reset flow.
(Agent Mode)
Hard Reset Flow
PORESET
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
HRESET
(Output)
Because the device does not sample the reset configuration input signals
(CFG_RESET_SOURCE, CFG_CLKIN_DIV) during a hard reset flow,
setting a new value on those signals (other than that set during power-on
reset) has no effect.
(Input)
(Input)
TRST
SYS_CLK_IN/PCI_CLK
Section 4.3.3, “Loading the Reset Configuration Words.”
Min. 32
Stable clock
cycles
Figure 4-1. Power-On Reset Flow
configuration words
Start loading reset
NOTE
locked (no
indication)
PLLs are
external
After the configuration
Duration depends on
configuration words.
End loading reset
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