MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1181

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.3.2.27, 16-41
16.5.6, 16-59
16.6.1, 16-65
17.3.1.5, 17-9
17.5.5, 17-22
18.3.1.3, 18-7
18.3.1.3, 18-8
A.2
Major changes to the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual,
from Revision 0 to Revision 1 are as follows:
Section, Page
1.1, 1-4
Freescale Semiconductor
29
Changes From Revision 0 to Revision 1
USB_EN
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In Table 16-36, bit 29, changed the description to read as follows:
In Figure 16-40, for RL, changed to bits 31–28, C to bit 27, and Maximum Packet
Length to bits 26–16.
In first paragraph, first sentence, removed ‘as illustrated in Table 25’. Replaced
the second with the following:
After a hardware reset, only the operational registerswill be at their default values.
Deleted Table 16-63 and renumbered the rest of the tables in the chapter.
Table 17-8, changed the last sentence in the DATA description to read:
Note that in both master receive and slave receive modes, the very first read is
always a dummy read.
In second paragraph, removed the the sentence: ‘For 1-byte transfers, a dummy
read should be performed by the interrupt service routine (see Figure 17-11).’
In Table 18-8, replaced the table with 133 and 167 MHz information.
In the last paragraph, changed item 1 as follows:
1. The input clock frequency (ICF) is divided by the actual frequency input (AFI)
Throughout book, removed ‘MPC8313E and MPC8313 specific,’ text. Removed
LSYNC_OUT and LSYNC_IN.
Throughout book—removed internal signal LBC_PM_REF_10 references.
Throughout book—fixed the direction of signals in figures and tables.
Throughout chapter, replaced ‘On-chip USB-2.0 full-speed/high-speed PHY with
ULPI (UTMI + low-pin interface),’ with the following:
On-chip USB-2.0 full-speed/high-speed PHY with UTMI
UTMI mode: This bit is used to enable the USB interface. It must be set before setting RS bit in
USB CMD register.
1 Enable
0 Disable
ULPI mode: In safe mode, all USB interface signals are put into input mode or driven inactive,
except for SUSPEND_STP which is driven high. Also, the input signal DIR is forced to appear high
to the controller. This prevents any start-up problems that otherwise could occur if the PHY and
the controller take significantlly different times to complete power-on reset.
1 Normal operation
0 Safe mode
to get the correct divisor value (ICF/AFI, where AFI = baud
rate × 16 × divisor).
Changes
Revision History
A-23