MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1042

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
Detected] when it receives MDATA or DATA0/1 with a data payload of more than 192 bytes. The
following responses have the noted effects:
If Test A succeeds, but Test B fails, it means that one or more of the complete-splits have been skipped.
The host controller sets the Missed Micro-Frame status bit and clears the Active bit.
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ERR. The full-speed transaction completed with a time-out or bad CRC and this is a reflection of
that error to the host. The host controller sets the ERR bit in the siTD[Status] field and clears the
Active bit.
Transaction Error (XactErr). The complete-split transaction encounters a Timeout, CRC16 failure,
etc. The siTD[Status] field XactErr field is set and the complete-split transaction must be retried
immediately. The host controller must use an internal error counter to count the number of retries
as a counter field is not provided in the siTD data structure. The host controller will not retry more
than two times. If the host controller exhausts the retries or the end of the micro-frame occurs, the
Active bit is cleared.
DATAx (0 or 1). This response signals that the final data for the split transaction has arrived. The
transfer state of the siTD is advanced and the Active bit is cleared. If the Bytes To Transfer field
has not decremented to zero (including the reception of the data payload in the DATAx response),
then less data than was expected, or allowed for was actually received. This short packet event does
not set the USB interrupt status bit (USBSTS[UI]) to a one. The host controller will not detect this
condition.
NYET (and Last). On each NYET response, the host controller also checks to determine whether
this is the last complete-split for this split transaction. Last was defined in Section Periodic
Interrupt - Do Complete Split. If it is the last complete-split (with a NYET response), then the
transfer state of the siTD is not advanced (never received any data) and the Active bit is cleared.
No bits are set in the Status field because this is essentially a skipped transaction. The transaction
translator must have responded to all the scheduled complete-splits with NYETs, meaning that the
start-split issued by the host controller was not received. This result should be interpreted by
system software as if the transaction was completely skipped. The test for whether this is the last
complete split can be performed by XORing C-mask with C-prog-mask. A zero result indicates
that all complete-splits have been executed.
MDATA (and Last). See above description for testing for Last. This can only occur when there is
an error condition. Either there has been a babble condition on the full-speed link, which delayed
the completion of the full-speed transaction, or software set up the S-mask and/or C-masks
incorrectly. The host controller must set the XactErr bit and clear the Active bit.
NYET (and not Last). See above description for testing for Last. The complete-split transaction
received a NYET response from the transaction translator. Do not update any transfer state (except
for C-prog-mask) and stay in this state.
MDATA (and not Last). The transaction translator responds with an MDATA when it has partial
data for the split transaction. For example, the full-speed transaction data payload spans from
micro-frame X to X+1 and during micro-frame X, the transaction translator responds with an
MDATA and the data accumulated up to the end of micro-frame X. The host controller advances
the transfer state to reflect the number of bytes received.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor