MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 214

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.2.4
5.2.4.1
The IMMR window contains configuration, control, and status registers, as well as internal device memory
arrays. The internal memory map occupies a 1-Mbyte region of memory space. Its location is
programmable using the internal memory map register (IMMR). The default base address for the internal
memory map register is 0xFF40_0000. Because IMMRBAR is at offset 0x0 from the beginning of the
local access registers, IMMRBAR always points to itself.
5.2.4.1.1
Updates to IMMRBAR that relocate the entire 1-Mbyte region of the internal memory block require
special treatment. The effect of the update must be guaranteed to be visible by the mapping logic before
an access to the new location is seen. To make sure this happens, the following guidelines should be
followed:
The IMMRBAR is shown in
5-6
Offset 0x00
Reset
Reset
•
•
W
W
R
R
IMMRBAR should be updated during initial configuration of the device when only one host or
controller has access to the device as follows:
When the e300 core is writing to IMMRBAR, it should use the following sequence:
16
1
0
– If an external host on PCI is configuring the device, it should set IMMRBAR to the desired
– If the core is initializing the device, it should set IMMRBAR to the desired final location
– Read the current value of IMMRBAR using a load word instruction followed by an isync.
– Write the new value to IMMRBAR.
– Perform a load of an address that does not access configuration space or the on-chip SRAM,
– Read the contents of IMMRBAR from its new location, followed by another isync.
Local Access Register Descriptions
Internal Memory Map Registers Base Address Register (IMMRBAR)
Figure 5-2. Internal Memory Map Registers’ Base Address Register (IMMRBAR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
final location before the e300c3 core is released to boot.
before enabling other I/O devices to access the device.
This forces all accesses to configuration space to complete.
but has an address mapping already in effect (for example, boot ROM). Follow this load
with an isync.
Updating IMMRBAR
1
1
1
Figure
1
5-2.
BASE_ADDR
1
1
1
All zeros
—
0
1
0
11
0
12
0
Access: User Read/Write
Freescale Semiconductor
0
—
0
15
31
0