MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 475

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x0_50B4
Reset
Reset
10.3.1.10 Transfer Error Check Disable Register (LTEDR)
The transfer error check disable register (LTEDR), shown in
checking. Note that control of error/event checking is independent of control of reporting of errors/events
(LTEIR) through the interrupt mechanism.
Table 10-17
Freescale Semiconductor
10–11
Bits
3–4
6–7
12
W
W
0
1
2
5
8
9
R
R
BMD FCTD PARD
16
0
WARA Write after read atomic (WARA) error checking disable.
RAWA Read after write atomic (RAWA) error checking disable.
Name
FCTD FCM command time-out disable
PARD ECC error checking disabled.
WPD
BMD
CSD
—
—
—
describes LTEDR fields.
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Bus monitor disable
0 Bus monitor is enabled.
1 Bus monitor is disabled, but internal bus time-outs can still occur.
0 FCM command timer is enabled.
1 FCM command time-out is disabled, but internal FCM command timer can terminate command waits.
0 ECC error checking is enabled.
1 ECC error checking is disabled.
Reserved
Write protect error checking disable.
0 Write protect error checking is enabled.
1 Write protect error checking is disabled.
Reserved
0 WARA error checking is enabled.
1 WARA error checking is disabled.
0 RAWA error checking is enabled.
1 RAWA error checking is disabled.
Reserved
Chip select error checking disable.
0 Chip select error checking is enabled.
1 Chip select error checking is disabled.
2
Figure 10-14. Transfer Error Check Disable Register (LTEDR)
3
—
4
Table 10-17. LTEDR Field Descriptions
WPD
5
6
—
—
7
All zeros
All zeros
WARA RAWA
Description
8
Figure
9
10-14, is used to disable error/event
10
—
11
CSD
12
Enhanced Local Bus Controller
13
29
Access: Read/Write
UCCD
—
30
10-27
CCD
15
31