MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1009

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

USBSTS[AS] to determine when the asynchronous schedule has made the desired transition. Software
must not modify USBCMD[ASE] unless the value of USBCMD[ASE] equals that of the USBSTS[AS]
(asynchronous schedule status).
The asynchronous schedule is used to manage all Control and Bulk transfers. Control and Bulk transfers
are managed using queue head data structures. The asynchronous schedule is based at the
ASYNCLISTADDR register. The default value of the ASYNCLISTADDR register after reset is undefined
and the schedule is disabled when USBCMD[ASE] is cleared.
Software may only write this register with defined results when the schedule is disabled, for example,
USBCMD[ASE] and the USBSTS[AS] are cleared. System software enables execution from the
asynchronous schedule by writing a valid memory address (of a queue head) into this register. Then
software enables the asynchronous schedule by setting USBCMD[ASE]. The asynchronous schedule is
actually enabled when USBSTS[AS] is set.
When the host controller begins servicing the asynchronous schedule, it begins by using the value of the
ASYNCLISTADDR register. It reads the first referenced data structure and begins executing transactions
and traversing the linked list as appropriate. When the host controller completes processing the
asynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in the
ASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the first data
structure that is serviced. This provides round-robin fairness for processing the asynchronous schedule.
A host controller completes processing the asynchronous schedule when one of the following events
occur:
The queue heads in the asynchronous list are linked into a simple circular list as shown in
Queue head data structures are the only valid data structures that may be linked into the asynchronous
schedule. An isochronous transfer descriptor (iTD or siTD) in the asynchronous schedule yields undefined
results.
The maximum packet size field in a queue head is sized to accommodate the use of this data structure for
all non-isochronous transfer types. The USB Specification, Revision 2.0 specifies the maximum packet
sizes for all transfer types and transfer speeds. System software should always parameterize the queue head
data structures according to the core specification requirements.
16.6.9.1
This is a software requirement section. There are two independent events for adding queue heads to the
asynchronous schedule. The first is the initial activation of the asynchronous list. The second is inserting
a new queue head into an activated asynchronous list.
Activation of the list is simple. System software writes the physical memory address of a queue head into
the ASYNCLISTADDR register, then enables the list by setting USBCMD[ASE] to a one.
When inserting a queue head into an active list, software must ensure that the schedule is always coherent
from the host controllers' point of view. This means that the system software must ensure that all queue
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The end of a micro-frame occurs.
The host controller detects an empty list condition
The schedule has been disabled through USBCMD[ASE].
Adding Queue Heads to Asynchronous Schedule
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Universal Serial Bus Interface
Figure
16-44.
16-81