MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 244

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.4.6
5.4.6.1
The software watchdog timer is enabled (by the default value of SWCRR[SWEN]) after reset. The
following initialization sequence of WDT is required:
5.5
The following sections describe the theory of operation of the real time clock module (RTC) including a
definition of the external signals and the functions it serves. Additionally, the configuration, control, and
status registers are described. Note that individual chapters in this reference manual describe additional
specific initialization aspects for each individual block.
5.5.1
The device platform provides a real time clock (RTC) timer suitable for timestamping or time and calendar
generation. It can maintain a one-second count which is unique over a period of approximately 136 years.
The RTC can be initialized by software with an initial count value using the real time counter load register
(RTLDR). It can also be programmed to generate an interrupt every second. The real time counter control
register (RTCTR) is used to enable or disable the various timer functions. The real time counter event
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— Reset mode (SWCRR[SWRI] = 1).
— Interrupt mode (SWCRR[SWRI] = 0).
WDT prescaled/non-prescaled clock mode
The WDT counter clock can be prescaled by programming the SWCRR[SWPR] bit that controls
the divide-by-65,536 of the WDT counter.
— Prescale mode (SWCRR[SWPR] = 1)
— Non-prescale mode (SWCRR[SWPR] = 0)
WDT disabling
If the software watchdog timer is not needed, the user must clear SWCRR[SWEN] bit to disable
the WDT not later than its timer times out (~12.8 sec. for a 333-MHz system clock).
WDT initial servicing
If the software watchdog timer is to be used, the special service sequence, described in
Section 5.4.5.1, “Software Watchdog Timer Unit,”
later than the first WDT time-out (~12.8 sec. for a 333-MHz system clock).
Subsequently, periodical WDT servicing should be performed according to the programming
guidelines given in
Real Time Clock Module (RTC)
Software watchdog timer causes a hard reset (this is the default value after hard reset).
Software watchdog timer causes a machine check interrupt to the core.
The WDT clock is prescaled.
The WDT clock is not prescaled.
Initialization/Application Information
RTC Overview
WDT Programming Guidelines
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 5.4.5.1, “Software Watchdog Timer Unit.”
must be executed after system reset and not
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