MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 309

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

6.2.5
Arbiter mask register (AMR) is used to mask interrupts or reset requests. Setting a mask bit enables the
corresponding interrupt or reset request; clearing a bit masks it. Regular interrupts, MCP interrupts and
reset requests can be masked by AMR register.
Table 6-6
6.2.6
Arbiter event attributes register (AEATR) reports the type of transaction that causes error, which is
specified in the event register. See
AEATR is cleared only by power-on reset. The attributes of the first error event are stored. Note that this
means that AEATR does not change its value when AER is not clear. As AEATR is not affected by soft or
hard reset, software can read this register and determine the cause of the bus failure, even if the failure
caused a deadlock situation. Refer to
Freescale Semiconductor
Offset 0x14
Reset
0–25
Bits
26
27
28
29
30
31
W
R
0
describes AMR fields.
Name
ETEA
ECW
RES
DTO
ATO
AO
—
Arbiter Mask Register (AMR)
Arbiter Event Attributes Register (AEATR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write reserved, read = 0
Transfer error. Detection of transfer error by one of the slaves interrupt mask bit.
0 Detection of transfer error by one of the slaves interrupt disabled.
1 Detection of transfer error by one of the slaves interrupt enabled.
Reserved transfer type.Transaction with reserved transfer type interrupt mask bit.
0 Transaction with reserved transfer type interrupt disabled.
1 Transaction with reserved transfer type interrupt enabled.
External control word transfer type.Transaction with external control word transfer type interrupt mask bit.
0 Transaction with external control word transfer type interrupt disabled.
1 Transaction with external control word transfer type interrupt enabled.
Address only transfer type. Transaction with address only transfer type interrupt mask bit.
0 Transaction with address only transfer type interrupt disabled.
1 Transaction with address only transfer type interrupt enabled.
Data time out. Data tenure time out interrupt mask bit.
0 Data tenure time out interrupt disabled.
1 Data tenure time out interrupt enabled.
Address time out. Address tenure time out interrupt mask bit.
0 Address tenure time out interrupt disabled.
1 Address tenure time out interrupt enabled.
Figure 6-5. Arbiter Mask Register (AMR)
Section 6.2.3, “Arbiter Event Register (AER),”
Table 6-6. AMR Field Descriptions
Section 6.4.2, “Error Handling Sequence,”
—
Figure 6-5
All zeros
Description
shows the fields of AMR.
25
ETEA RES ECW AO DTO ATO
26
for more information.
for more information.
27
Access: User read/write
Arbiter and Bus Monitor
28
29
30
31
6-7