MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 854

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.6.1.3
This section describes the reduced gigabit media-independent interface (RGMII) intended to be used
between the PHYs and the GMII MAC. The RGMII is an alternative to the IEEE802.3u MII, the
IEEE802.3z GMII. The RGMII reduces the number of signals required to interconnect the MAC and the
PHY from a maximum of 28 signals (GMII) to 15 signals (GTX_CLK125 included) in a cost effective and
technology independent manner. To accomplish this objective, the data paths and all associated control
signals are multiplexed using both edges of the clock. For gigabit operation, the clocks operate at 125MHz,
and for 10/100 operation, the clocks operate at 2.5 MHz or 25 MHz, respectively. Note that the
GTX_CLK125 input must be provided at 125 MHz for an RGMII interface, regardless of operation speed
(1 Gbps, 100 Mbps, or 10 Mbps).
media-independent interface and the signals required to establish the gigabit Ethernet controllers’ module
connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a
9/22/00.
15-136
2
The management signals (MDC and MDIO) are common to all of the Ethernet controllers module
connections in the system, assuming that each PHY has a different management address.
eTSEC
Reduced Gigabit Media-Independent Interface (RGMII)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reference Clock (TSEC n _TX_CLK)
Receive Control (RX_DV, RX_ER)
Figure 15-128. eTSEC-RMII Connection
Transmit Data (TSEC n _TXD[1:0])
Receive Data (TSEC n _RXD[1:0])
Management Data Clock
Figure 15-129
Management Data I/O
Transmit Control (TX_EN)
depicts the basic components of the gigabit reduced
2
(MDIO)
2
(MDC)
Ethernet
RMII
PHY
Freescale Semiconductor
Medium