MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 542

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.5.4.1
An example of configuring FCM to execute a soft reset command to large-page NAND Flash is shown in
Table
by writing FMR[OP] = 10, and issuing a special operation to the bank. At the conclusion of the sequence,
eLBC will issue a command complete interrupt (LTESR[CC]) if interrupts are enabled.
10.5.4.2
An example of configuring FCM to execute a status read command to large-page NAND Flash is shown
in
Flash status into register MDR[AS0]. The sequence is initiated by writing FMR[OP] = 10 and issuing a
special operation to the bank. At the conclusion of the sequence, eLBC will issue a command complete
interrupt (LTESR[CC]) if interrupts are enabled.
10.5.4.3
An example of configuring FCM to execute a status ID command to large-page NAND Flash is shown in
Table
a dummy address prior to the sequence, and then to receive the first 4 bytes of ID during the sequence. The
sequence is initiated by writing FMR[OP] = 10, and issuing a special operation to the bank. At the
10-94
Table
10-44. This sequence does not require use of the shared FCM buffer RAM. The sequence is initiated
10-46. This sequence does not require use of the shared FCM buffer RAM, but uses MDR to set up
10-45. This sequence does not require use of the shared FCM buffer RAM, but reads the NAND
Register
Register
FBCR
FBCR
FBAR
FBAR
FPAR
FPAR
MDR
MDR
NAND Flash Soft Reset Command Sequence Example
FCR
NAND Flash Read Status Command Sequence Example
FCR
NAND Flash Read Identification Command Sequence Example
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
FIR
FIR
Table 10-45. FCM Register Settings for Status Read (OR n [PGS] = 1)
Table 10-44. FCM Register Settings for Soft Reset (OR n [PGS] = 1)
Initial Contents
Initial Contents
0xFF000000
0x40000000
0x70000000
0x4B000000
—
—
—
—
—
—
—
—
CMD0 = 0xFF = reset command; other commands unused
unused
unused
unused
unused
OP0 = CM0 = command 0;
OP1–OP7 = NOP
CMD0 = 0x70 = read status command; other commands unused
unused
unused
unused
Status returned in AS0
OP0 = CM0 = command 0;
OP1 = RS = read status to MDR;
OP2–OP7 = NOP
Description
Description
Freescale Semiconductor