MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 707

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

transfers between the host and the EUs are moderated by the controller. Some of the main functions of the
controller are as follows:
14.6.1
Assignment of a EU to the channel is done dynamically.
checks to see if the requested EU is available, and if it is, the controller grants the channel assignment of
the EU.
When requested, the controller will assert the grant signal pertaining to the request from the channel. The
grant signal will remain asserted until the channel is done and releases the EU.
In some cases, the channel may request two EUs. The channel will do this by first requesting the primary
EU, then requesting the secondary EU. Once the controller has granted both EUs, the channel is then
capable of requesting that the secondary EU snoop the bus. Snooping status is indicated in the MI and MO
bits of
In all cases, the controller assigns the primary EU to the requesting channel as the EUs become available.
The controller does not wait until both EUs are available before issuing grants to the channel which is
requesting two EUs.
14.6.2
The controller in the SEC (refer to) has the ability to be a bus master or a slave. This means that the
controller can issue read and write commands to the bus, and it can also be written to and read from by the
host.
The controller is the sole bus master in the SEC. All other modules are slave-only devices. A channel may
request access to system resources including the bus. In these cases, the channel must provide the starting
address of the transfer for the bus(es) requested. All subsequent addresses are generated by the controller.
All addresses will be sequential.
14.6.2.1
The controller attempts to maximize utilization of the system bus by grouping outstanding bus requests
from the channel by request type (read or write). The controller will perform all write requests to the
system bus, followed by all read requests, then repeat.
1. The security engine in the MPC8313E is a single-channel implementation, but other variants of the SEC have been
implemented with 1, 2, and 4 channels. Although not necessary for a single-channel SEC, dynamic assignment of EUs to the
channel is maintained to improve software compatibility with other SEC-enhanced processors.
Freescale Semiconductor
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Table
Provide arbitration for bus access and control bus accesses
Control the internal bus accesses to the EUs
Assign EUs to the channel
Monitor interrupts from the channel and EUs and pass to host
Realign read and write data to the proper byte alignment
Assignment of EUs to Channel
Bus Interface
14-32.
Arbitration for Use of the Controller and Buses
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
The channel requests an EU, the controller
Security Engine (SEC) 2.2
14-65