MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 640

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
Figure 13-53
error.
As an initiator, the PCI controller attempts to complete the transaction on the PCI bus if a data parity error
is detected and sets the data-parity-reported bit in the configuration space status register. If a data parity
error occurs on a read transaction, the PCI controller aborts the transaction internally. As a target, the PCI
controller completes the transaction on the PCI bus even if a data parity error occurs. If parity error occurs
during a write to system memory, the transaction completes on the PCI bus, but is aborted internally,
insuring that potentially corrupt data does not go to memory.
When the PCI controller asserts PCI_SERR, it sets the signaled-system-error bit in the configuration space
status register. Additionally, if the error is an address parity error, the parity-error-detected bit is set;
reporting an address parity error on PCI_SERR is conditioned on the parity-error-response bit being
enabled in the command register. PCI_SERR is asserted when the PCI controller detects an address parity
error while acting as a target. The system error is passed to the PCI controller’s interrupt processing logic
to assert MCP.
PCI_SERR or where the PCI controller, acting as an initiator, checks for the assertion of PCI_SERR
signaled by the target detecting an address parity error.
As a target that asserts PCI_SERR on an address parity, the PCI controller completes the transaction on
the PCI bus, aborting internally if the transaction is a write to system memory. If PCI_PERR is asserted
during a PCI controller write to PCI, the PCI controller attempts to continue the transfer, allowing the
target to abort/disconnect if desired. If the PCI controller detects a parity error on a read from PCI, the PCI
controller aborts the transaction internally and continues the transfer on the PCI bus, allowing the target to
abort/disconnect if desired.
13-58
shows the possible assertion points for PCI_PERR if the PCI controller detects a data parity
PCI_CBE[3:0]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCI_DEVSEL
PCI_AD[31:0]
PCI_FRAME
Figure 13-53
PCI_PERR
PCI_SERR
PCI_TRDY
PCI_IRDY
PCI_CLK
PCI_PAR
shows where the PCI controller could detect an address parity error and assert
ADDR
CMD
Figure 13-53. PCI Parity Operation
BEs
DATA
ADDR
CMD
DATA
BEs
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