MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 941

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
Bits
9–8
3–2
7
6
5
4
Name
ASP
ASE
PSE
IAA
LR
FS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Asynchronous schedule park mode count. The reset value of this field is always 0x3 after the USBDR
controller is configured as a host by writing 0x3 to USBMODE; else, the reset value is always 0x0. It
contains a count of the number of successive transactions the host controller is allowed to execute from a
high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous
schedule. Valid values are 0x1H to 0x3H. Software must not write a zero to this field when ASPE is set as
this will result in undefined behavior.
Light host/device controller reset (OPTIONAL). Not implemented. Always 0.
Interrupt on async advance doorbell. Used as a doorbell by software to tell the USB DR controller to issue
an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the
doorbell.
When the controller has evicted all appropriate cached schedule states, it sets USBSTS[AAI]. If
USBINTR[AAE] is set, the host controller will assert an interrupt at the next interrupt threshold.
The controller clears this bit after it has set USBSTS[AAI]. Software should not set this bit when the
asynchronous schedule is inactive. Doing so will yield undefined results.
This bit is only used in host mode. Setting this bit when the USB DR module is in device mode is selected
will result in undefined results.
Asynchronous schedule enable. Controls whether the controller skips processing the asynchronous
schedule. Only used in host mode.
0 Do not process the asynchronous schedule
1 Use the ASYNCLISTADDR register to access the asynchronous schedule.
Periodic schedule enable. Controls whether the controller skips processing the periodic schedule. Only
used in host mode.
0 Do not process the periodic schedule.
1 Use the PERIODICLISTBASE register to access the periodic schedule.
Frame list size. Together with bit 15 these bits make the FS[2:0] field. This field is read/write only if
programmable frame list flag in the HCCPARAMS registers is set to 1. This field specifies the size of the
frame list that controls which bits in FRINDEX should be used for the frame list current index. Only used in
host mode. Note that values below 256 elements are not defined in the EHCI specification.
000 1024 elements (4096 bytes)
001 512 elements (2048 bytes)
010 256 elements (1024 bytes)
011 128 elements (512 bytes)
100 64 elements (256 bytes)
101 32 elements (128 bytes)
110 16 elements (64 bytes)
111 8 elements (32 bytes)
Table 16-10. USBCMD Register Field Descriptions (continued)
Description
Universal Serial Bus Interface
16-13