MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 181

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 4-11
Freescale Semiconductor
9–11
Bits
6–7
0
1
2
3
4
5
8
BOOTSEQ
PCIHOST
COREDIS
ROMLOC
PCIARB
SWEN
Name
defines the reset configuration word high bit fields.
BMS
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCI host mode.
See
Reserved, should be cleared.
PCI internal arbiter mode. Enables the on-chip PCI arbiter.
0 On-chip PCI arbiter is disabled. External arbitration is required.
1 On-chip PCI arbiter is enabled.
The value of PCIARB also defines the function of the PCI arbitration signals that are multiplexed with
CompactPCI signals, as follows:
Reserved, should be cleared.
Core disable mode. Specifies the e300 core mode out of reset. If COREDIS is set, the core cannot fetch
boot code until it is configured by an external master. The external master frees the core to boot by
clearing the COREDIS bit in the arbiter configuration register as described in
Configuration Register (ACR).”
This bit must be set when the boot sequencer is enabled to initiate the device (BOOTSEQ is not 0b00).
Otherwise, unpredictable behavior occurs.
0 The core can boot without waiting for configuration by an external master.
1 Core boot holdoff mode. The core is prevented from booting until it is configured by an external
Boot memory space.
See
Boot sequencer configuration.
See
Software watchdog enable. Selects whether the software watchdog is enabled to start counting down
immediately when coming out of reset. The user can override this value by writing to the system
watchdog control register (SWCRR[SWEN]) during system initialization.
0 Disabled
1 Enabled
Boot ROM interface location.
This bit combined with bit RLEXT determines where the device boots from. See
ROM Location,”
master.
Section 4.3.2.2.1, “PCI Host/Agent
Section 4.3.2.2.2, “Boot Memory Space
Section 4.3.2.2.3, “Boot Sequencer
Table 4-11. Reset Configuration Word High Bit Settings
for more information.
Pin Function When
CPCI_HS_ENUM
CPCI_HS_LED
CPCI_HS_ES
PCIARB = 0
Configuration,” for more information.
Configuration,” for more information.
Description
(BMS),” for more information.
Pin Function When
PCIARB = 1
PCI_REQ[1]
PCI_GNT[1]
PCI_GNT[2]
Reset, Clocking, and Initialization
Section 6.2.1, “Arbiter
Section 4.3.2.2.4, “Boot
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