MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 502

Manufacturer Part Number

MPC8313ZQADDC

Microprocessors - MPU 8313 REV2.2 PB NO ENC

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MPC8313ZQADDC

Manufacturer:

Freescale Semiconductor

Enhanced Local Bus Controller

The timing of the LOE is affected only by TRLX. It always asserts and negates on the rising edge of the

bus clock. LOE asserts either on the rising edge of the bus clock after LCSn is asserted or coinciding with

LCSn (if XACS = 1 and ACS = 10 or ACS = 11). Accordingly, assertion of LOE can be delayed (along

with the assertion of LCSn) by programming TRLX = 1. LOE negates on the rising clock edge coinciding

with LCSn negation

Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose

some combination of ORn[TRLX,EHTR]. Any access following a read access to the slower memory bank

is delayed by the number of clock cycles specified in

cycle. The final bus turnaround cycle is automatically inserted by the eLBC for reads, regardless of the

setting of OR

Figure 10-41. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Output Enable (LOE) Timing

Extended Hold Time on Read Accesses

Latched Address 1

Bus turnaround

in addition to any existing bus turnaround

Latched Address 2

Freescale Semiconductor