MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 293

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The e300 device driver runs locally on the e300 processor and interfaces to PMC internally
At initial power-up (POR), external PCI host software is required to determine the power management
capabilities of all agents and initialize their PME context, including the PME support bits. To support PME
signaling the PCI device driver must set the PCI function's PCIPMR1[PME_En] register bit and the
PCIPMR1[PME_Status] register bit (clearing the PME_Status bit). The e300 device driver must also set
the PMC's PMCCR1[PME_EN].
Steps to power down the device to the lowest power state, D3Warm, are as follows.
Freescale Semiconductor
1. Configure IPIC registers to mask interrupts to core.
2. Disable MSR[EE] to disable external interrupts. The software must complete servicing any
3. An e300 driver routine programs PMC to allow wake-up on one of the PMC wake-up events
4. The PCI device driver executes code to save any MPC8313E context that would not otherwise
5. PCI device driver enables the PCI function to generate PCI_PME, then programs the D3Hot state
6. This PCI Configuration PowerState register setting is detected and also reflected into the
7. An e300 interrupt routine detects PMC's PMCCR1[NEXT_STATE] notification and begins the
pending interrupts before doing so.
(eTSEC magic packet, USB, GPIO internal timer, external interrupt) by writing a “1” in the
appropriate PMCMR[] mask register bit.
survive the transition to the new power state (any MPC8313E context beyond what e300 software
would configure on reset).
into the PCI function's PCIPMR1[Power_State] field.
Note: In order for the device to assert PCI_PME, both PCIPMR1[PME_EN] and
PMCCR1[PME_EN] must be set.
PMCCR1[NEXT_STATE] register. This change generates an interrupt to the e300 through the
IPIC.
Note: PCI PM 1.2 specification requires PCI’s PCIPMR1[Power_State] field to reflect the current
state until the PCI agent is in the next state. Therefore the PCIPMR1[Power_State] field will still
read as 00b until the e300 updates the power state (see Step 11)
Note: The PMC is designed such that any time the PMCCR1[NEXT_STATE] field is different than
the PMCCR1[CURRENT_STATE] field and interrupt will be asserted to the e300 core via IPIC.
process of power down. It stops all of the masters on the CSB bus, including:
— Security engine (by not providing buffer descriptors to work on)
— eTSECs (gracefully stop through DMACTRL[GRS] and DMACTRL[GTS])
— USB (placing USB into suspend mode)
Note: that the PMC does not automatically sequence the device into low power mode when the
next_state bits are set to D3. This next_state change only generates an interrupt to the e300. the
e300 will then sequence the device into the requested low power mode.
Then the e300 enables any desired wake-up sources: eTSEC to wake on Magic Packet
reception by setting eTSEC MACCFG2[MPEN], USB link activity, GPIO transition, internal
timer expires, assertion of external interrupt.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
System Configuration
TM
5-85