MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1197

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Tenure. The period of bus mastership. There can be separate address bus tenures and data
Throughput. The measure of the number of instructions that are processed per clock
Time-division multiplex (TDM). A single serial channel used by several channels taking
Transaction. A complete exchange between two bus devices. A transaction is typically
Transfer termination. Signal that refers to both signals that acknowledge the transfer of
Translation lookaside buffer (TLB). A cache that holds recently-used
User mode. The operating state of a processor used typically by application software. In
Virtual address. An intermediate address used in the translation of an
Virtual memory. The address space created using the memory management facilities of
Way. A location in the cache that holds a cache block, its tags, and status bits.
Word. A 32-bit data element.
Write-back. A cache memory update policy in which processor write cycles are directly
Write-through. A cache memory update policy in which all processor write cycles are
bus tenures.
cycle.
turns.
comprised of an address tenure and one or more data tenures, which may overlap
or occur separately from the address tenure. A transaction may be minimally
comprised of an address tenure only.
individual beats (of both single-beat transfer and individual beats of a burst
transfer) and to signals that mark the end of the tenure.
user mode, software can access only certain control registers and can access only
user memory space. No privileged operations can be performed. Also referred to
as problem state.
a physical address.
the processor. Program access to virtual memory is possible only when it coincides
with
written only to the cache. External memory is updated only indirectly, for
example, when a modified cache block is
written to both the cache and memory.
physical
memory.
cast out
to make room for newer data.
effective address
page table
Glossary-9
entries.
to