MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1213

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Index
Freescale Semiconductor
queue heads, 16-47, 16-62
registers
signals, 16-3–16-5
split transaction isochronous transfer descriptor (siTD),
endpoint capabilities/characteristics, 16-63
horizontal link pointer, 16-62
managing control/bulk/interrupt transfers, 16-85
managing the QH[FrameTag] field, 16-103
transfer overlay, 16-65
by acronym, see Register Index
capability registers, 16-7
operational registers, 16-11
ULPI interface, 16-4
UTMI interface, 16-4
back link pointer, 16-56
buffer pointer list (plus), 16-55
endpoint capabilities/characteristics, 16-53
next link pointer, 16-53
transfer state, 16-54
buffer pointer list use for data streaming with qTDs,
ping control, 16-89
to the periodic schedule, 16-88
transfer complete interrupts, 16-88
16-47, 16-53
16-86
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
USB_CLK_IN signal, 4-3
User-level SPRs, 7-16
W
Watchdog timer (WDT), 5-29
Z
ZBT SRAM interface (LBC), 10-97, 10-102
split transactions, 16-90
block diagram, 5-29
features, 5-29
functional block diagram, 5-34
functional description, 5-33
memory map/register definition, 5-30
modes of operation, 5-30, 5-34
overview, 5-29
registers, 5-31–5-33
asynchronous transfers, 16-90
interrupt, 16-92
Do-Complete-Split state, 16-91
Do-Start-Split state, 16-91
execution state machine, 16-98
host controller operational model for FSTNs, 16-95
scheduling mechanisms, 16-92
software operational model for FSTNs, 16-97
tracking progress for interrupt transfers, 16-98
Index-15
W–Z