MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 962

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.2.16 USB Mode Register (USBMODE)—Non-EHCI
This register is not defined in the EHCI specification. This register controls the operating mode of the
module.
16-34
31–5
Bits
1–0
4
3
2
Offset 0x2_31A8
Reset
W
SLOM Setup lockout mode. In device mode, this bit controls behavior of the setup lock mechanism. See
Name
R
SDIS
CM
—
—
31
Reserved, should be cleared.
Stream disable
In host mode, setting this bit ensures that overruns/underruns of the latency FIFO are eliminated for low
bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream
disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the
USB.
Note that time duration to pre-fill the FIFO becomes significant when stream disable is active. See
TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature.
Also note that in systems with high system bus utilization, setting this bit will ensure no overruns or underruns
during operation, at the expense of link utilization. For those who desire optimal link performance, SDIS can be
left clear, and the rules used under the description of the TXFILLTUNING register to limit underruns/overruns.
1 Active.
0 Inactive.
In device mode, setting this bit disables double priming on both RX and TX for low bandwidth systems. This
mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double
buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems.
Note that in high-speed mode, all packets received will be responded to with a NYET handshake when stream
disable is active.
Section 16.8.3.5, “Control Endpoint Operation Model.”
1 Setup lockouts off. DCD requires use of setup data buffer tripwire in USBCMD (SUTW).
0 Setup lockouts on
Reserved, should be cleared.
Controller mode
This register can only be written once after reset. If it is necessary to switch modes, software must reset the
controller by writing to USBCMD[RST] before reprogramming this register.
00 Idle (default for combination host/device).
01 Reserved, should be cleared.
10 Device controller (default for device only controller).
11 Host controller (default for host only controller).
Defaults to the idle state and needs to be initialized to the desired operating mode after reset.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 16-25. USBMODE Register Field Descriptions
Figure 16-22. USB Mode (USBMODE)
—
All zeros
Description
5
SDIS SLOM —
Freescale Semiconductor
4
Access: Read/Write
3
2
1
CM
0