MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 167

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Chapter 4
Reset, Clocking, and Initialization
The reset, clocking, and control signals offer many options for operating the device. Various modes and
features can be configured during hard reset or power-on reset. Most configurable features are loaded to
the device through a reset configuration word, and a few device signals are used as reset configuration
inputs during the reset sequence.
4.1
The following sections describe the reset and clock signals in detail.
4.1.1
Table 4-1
the signals that also function as reset configuration signals.
Freescale Semiconductor
PORESET
HRESET
Signal
External Signals
describes the reset signals of the device.
Reset Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
I/O Hard reset. Causes the device to abort all current internal and external transactions and set most
I
Power-on reset. Initiates the power-on reset flow that resets the device and configures various
attributes of the device, including its clock modes.
registers to their default values. HRESET can be asserted completely asynchronously with respect to
all other signals. The device can detect an external assertion of HRESET while the device is not
asserting hard reset. HRESET is an open-drain signal.
State Meaning Asserted—An external agent has triggered a power-on reset sequence.
State Meaning Asserted—An external agent or internal hardware has triggered a hard reset. The
Requirements An open-drain signal. An external pull-up is required.
Reset State Always input.
Reset State Output, driven low during power-on and hard reset flows. High impedance after reset
Timing See the hardware specifications for timing information.
Timing Assertion—Occur at any time, asynchronously to any clock.
Table 4-1. System Control Signals
Negated—No power-on reset.
internal hardware drives HRESET until the sequence completes.
Negated—No hard reset.
Negation—Must be asserted for at least 32 SYS_CLK_IN (PCI host mode) or
flow completes.
PCI_CLK (PCI agent mode) cycles.
Section 4.3.2, “Reset Configuration Words,”
Description
describes
4-1