MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1129

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

18.4.4
The following sections describe framing, parity, and overrun errors which may occur while data is
transferred on the UART bus. Each of the error bits are usually cleared, as described below, when the line
status register (ULSR) is read.
18.4.4.1
When an invalid STOP bit is detected, a framing error occurs and ULSR[FE] is set. Note that only the first
STOP bit is checked. In FIFO mode, ULSR[FE] is set when the character at the top of the FIFO detects a
framing error. An attempt to re-synchronize occurs after a framing error. The UART assumes that the
framing error (due to a logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit
overlapping with the next START bit. ULSR[FE] is cleared when ULSR is read or when a new character
is loaded into the URBR from the receiver shift register.
18.4.4.2
When unexpected parity values are encountered while receiving data, a parity error occurs and ULSR[PE]
is set. In FIFO mode, ULSR[PE] is set when the character with the error is at the top of the FIFO.
ULSR[PE] is cleared when ULSR is read or when a new character is loaded into the URBR.
18.4.4.3
When a new (overwriting character) STOP bit is detected and the old character is lost, an overrun error
occurs and ULSR[OE] is set. In FIFO mode, ULSR[OE] is set after the receiver FIFO is full (despite the
receiver FIFO trigger level setting) and a new character has been received into the internal receiver shift
register. Data in the FIFO is not overwritten; only the shift register data is overwritten. Therefore, the
interrupt occurs immediately. ULSR[OE] is cleared when ULSR is read.
18.4.5
The UARTs use an alternate mode (FIFO mode) to relieve the processor core from excessive software
overhead. The FIFO control register (UFCR) is used to enable and clear the receiver and transmitter FIFOs
and set the FIFO receiver trigger level UFCR[RTL] to control the received data available interrupt
UIER[ERDAI].
The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of the
receiver FIFO. UDSR[TXRDY] indicate when the transmitter FIFO is full. When in FIFO mode, data
written to UTHR is placed into the transmitter FIFO. The first byte written to UTHR is the first byte onto
the UART bus.
18.4.5.1
In FIFO mode, the UIER[ERDAI] is set when a time-out interrupt occurs. A receive data time-out
generates a maskable interrupt condition (through UIER[ERDAI]). See
Enable Registers (UIER1 and UIER2)”.
Freescale Semiconductor
Errors
FIFO Mode
Framing Error
Parity Error
Overrun Error
FIFO Interrupts
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 18.3.1.4, “Interrupt
DUART
18-21