MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 364

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Integrated Programmable Interrupt Controller (IPIC)
8.5
The IPIC programmable register map occupies 256 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All IPIC registers are 32 bits wide and they are located on 32-bit address boundaries. Software can perform
byte, half-word or word accesses to any IPIC registers. All addresses used in this chapter are offsets from
the IPIC base, as defined in
Table 8-3
8-6
MCP_OUT OD Non-maskable Interrupt (machine check) request out. Active-low, open drain. When the IPIC is programmed
PCI_INTA OD Interrupt request out. Active-low, open drain. When the IPIC is programmed in core disable mode, this output
Signal
Offset
0x0C
0x1C
0x00
0x04
0x08
0x10
Memory Map/Register Definition
shows the memory map of the IPIC unit.
I/O
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
reflects the raw interrupts generated by on-chip sources. See
in core disable mode, this output reflects the mcp interrupts generated by on-chip sources. See
“Modes of
Meaning
Meaning
System global interrupt configuration register (SICFR)
System regular interrupt vector register (SIVCR)
System internal interrupt pending register (SIPNR_H)
System internal interrupt pending register (SIPNR_L)
System internal interrupt group A priority register (SIPRR_A)
System internal interrupt group D priority register (SIPRR_D)
Table 8-2. IPIC External Signals—Detailed Signal Descriptions (continued)
Timing Because external interrupts are asynchronous with respect to the system clock, both
Timing Because external interrupts are asynchronous with respect to the system clock, both
State
State
Operation.”
Asserted—At least one interrupt is currently being signalled to the external system.
Negated—Indicates no interrupt source currently routed to IRQ_OUT.
assertion and negation of IRQ_OUT occur asynchronously with respect to the interrupt source. All
timing given here is approximate.
Assertion—Internal interrupt source: 3 system bus clock cycles after the interrupt occurs. External
Negation—Follows interrupt source negation with the following delay:
Internal interrupt: 3 system bus clock cycles. External interrupt: 4 cycles.
Asserted—At least one machine check interrupt is currently being signalled to the external system.
Negated—Indicates no interrupt source currently routed to MCP_OUT.
assertion and negation of MCP_OUT occurs asynchronously with respect to the interrupt source.
All timing given here is approximate.
Assertion—Internal interrupt source: 2 system bus clock cycles after interrupt occurs. External
Negation—Follows interrupt source negation with the following delay:
Internal interrupt: 2 system bus clock cycles. External interrupt: 4 cycles.
Chapter 2, “Memory Map.”
interrupt source: 4 cycles after the interrupt occurs.
interrupt source: 4 cycles after interrupt occurs.
Table 8-3. IPIC Register Address Map
Register
Description
Section 8.3, “Modes of
Access
R/W
R/W
R/W
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0530_9770
0x0530_9770
Reset Value
Freescale Semiconductor
Operation,” for details.
8.5.3/8-11
8.5.3/8-11
8.5.4/8-13
8.5.5/8-14
8.5.1/8-7
8.5.2/8-9
Section/
Section 8.3,
Page