MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 67

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table
Number
15-126
15-127
15-128
15-129
15-130
15-131
15-132
15-133
15-134
15-135
15-136
15-137
15-138
15-139
15-140
15-141
15-142
15-143
15-144
15-145
15-146
15-147
15-148
15-149
15-150
15-151
15-152
15-153
15-154
15-155
15-156
15-157
15-158
15-159
15-160
15-161
15-162
15-163
15-164
15-165
15-166
Freescale Semiconductor
CR Field Descriptions ....................................................................................................... 15-124
SR Descriptions................................................................................................................. 15-125
ANA Field Descriptions.................................................................................................... 15-126
PAUSE Priority Resolution............................................................................................... 15-127
ANLPBPA Field Descriptions .......................................................................................... 15-128
ANEX Field Descriptions ................................................................................................. 15-129
ANNPT Field Descriptions ............................................................................................... 15-130
ANLPANP Field Descriptions .......................................................................................... 15-131
EXST Field Descriptions .................................................................................................. 15-132
JD Field Descriptions........................................................................................................ 15-133
TBICON Field Descriptions ............................................................................................. 15-134
GMII, MII, and RMII Signals Multiplexing ..................................................................... 15-139
MII and RMII Signals Multiplexing ................................................................................. 15-139
RGMII, TBI, and RTBI Signals Multiplexing .................................................................. 15-140
RGMII and RTBI Signals Multiplexing............................................................................ 15-141
RGMII Signals Multiplexing ............................................................................................ 15-142
Shared Signals................................................................................................................... 15-143
Steps for Minimum Register Initialization........................................................................ 15-144
Custom Preamble Field Descriptions................................................................................ 15-149
Received Preamble Field Descriptions ............................................................................. 15-150
Flow Control Frame Structure .......................................................................................... 15-154
Non-Error Transmit Interrupts .......................................................................................... 15-156
Non-Error Receive Interrupts............................................................................................ 15-156
Interrupt Coalescing Timing Threshold Ranges ............................................................... 15-157
Transmission Errors .......................................................................................................... 15-158
Reception Errors ............................................................................................................... 15-159
Tx Frame Control Block Description................................................................................ 15-162
Rx Frame Control Block Descriptions.............................................................................. 15-164
Supported Stack L2 Ethernet Headers .............................................................................. 15-166
Special Filer Rules ............................................................................................................ 15-170
Receive Queue Filer Interrupt Events ............................................................................... 15-170
Filer Table Example—802.1p Priority Filing ................................................................... 15-171
Filer Table Example—IP Diff-Serv Code Points Filing ................................................... 15-172
Filer Table Example—TCP and UDP Port Filing............................................................. 15-173
PTP Payload Special Fields............................................................................................... 15-180
Timestamp Insertion Programming Requirements ........................................................... 15-182
Tx Frame Control Block Description................................................................................ 15-184
Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......................................... 15-188
Receive Buffer Descriptor Field Descriptions .................................................................. 15-191
MII Interface Mode Signal Configuration ........................................................................ 15-193
Shared MII Signals............................................................................................................ 15-194
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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