MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1150

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

JTAG/Testing Support
The TDI and TDO signals input and output all instructions and data to the JTAG scan registers. JTAG
operations are controlled by the TAP controller through the TMS and TCK signals. Boundary-scan data is
latched by the TAP controller on the rising edge of the TCK signal. The TRST signal is specified as
optional by the IEEE 1149.1 specification, and is used to reset the TAP controller asynchronously. The
assertion of the TRST signal at power-on reset ensures that the JTAG logic does not interfere with the
normal operation of the device.
20.2.1
The JTAG signals are summarized in
Table 20-2
20-2
Signal
Name
TCK
TRST
TDI
TDO
TMS
TCK
•
•
TDI
Test reset (TRST)
Test clock (TCK)
I/O
Test clock
Test data input
Test data output
Test mode select
Test reset
I
I
shows detailed descriptions of the JTAG test signals.
External Signal Descriptions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
JTAG test clock.
JTAG test data input.
Meaning
Description
Meaning
Timing See IEEE 1149.1 specification for more details.
State
Timing See IEEE 1149.1 specification for more details.
State
Asserted/Negated—Should be driven by a free-running clock signal with a 30–70% duty cycle. Input
Asserted/Negated—The value present on the rising edge of TCK is clocked into the selected JTAG
Table 20-2. JTAG Test—Detailed Signal Descriptions
signals to the TAP are clocked in on the rising edge. Changes to the TAP output signals occur
on the falling edge. The test logic allows TCK to be stopped.
test instruction or data register. An unterminated input appears as a high signal level to the test
logic due to an internal pull-up resistor.
Functional
Debug
Block
Table 20-1. JTAG Test Signals Summary
Table
Clock for JTAG testing.
Serial input for instructions and data to the JTAG test
subsystem. Internally pulled up.
Serial data output for the JTAG test subsystem. High
impedance except when scanning out data.
Carries commands to the TAP controller for boundary
scan operations. Internally pulled up.
Resets the TAP controller asynchronously. Internally
pulled up.
20-1.
Description
Function
Freescale Semiconductor
impedance
Reset
Value
High
—
—
—
—
I/O
O
I
I
I
I