MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 33

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
16.8.3.3.2
16.8.3.4
16.8.3.4.1
16.8.3.5
16.8.3.5.1
16.8.3.5.2
16.8.3.5.3
16.8.3.5.4
16.8.3.6
16.8.3.6.1
16.8.3.6.2
16.8.4
16.8.4.1
16.8.4.2
16.8.5
16.8.5.1
16.8.5.2
16.8.5.3
16.8.5.4
16.8.5.5
16.8.5.6
16.8.6
16.8.6.1
16.8.6.2
16.8.6.3
16.9
16.9.1
16.9.1.1
16.9.1.2
16.9.1.3
16.9.1.4
16.9.1.5
16.9.1.5.1
16.9.1.5.2
16.9.1.5.3
16.9.1.5.4
16.9.1.5.5
16.9.2
16.9.3
16.9.4
16.9.5
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Deviations from the EHCI Specifications ................................................................. 16-148
Managing Queue Heads......................................................................................... 16-142
Managing Transfers with Transfer Descriptors ..................................................... 16-144
Servicing Interrupts................................................................................................ 16-147
Embedded Transaction Translator Function .......................................................... 16-148
Device Operation ................................................................................................... 16-152
Non-Zero Fields the Register File ......................................................................... 16-152
SOF Interrupt ......................................................................................................... 16-152
Embedded Design .................................................................................................. 16-153
Interrupt/Bulk Endpoint Operational Model ..................................................... 16-136
Control Endpoint Operation Model ................................................................... 16-138
Isochronous Endpoint Operational Model......................................................... 16-140
Queue Head Initialization .................................................................................. 16-143
Operational Model for Setup Transfers ............................................................. 16-143
Software Link Pointers ...................................................................................... 16-144
Building a Transfer Descriptor .......................................................................... 16-144
Executing a Transfer Descriptor ........................................................................ 16-145
Transfer Completion .......................................................................................... 16-145
Flushing/De-Priming an Endpoint ..................................................................... 16-146
Device Error Matrix........................................................................................... 16-146
High-Frequency Interrupts................................................................................. 16-147
Low-Frequency Interrupts ................................................................................. 16-147
Error Interrupts .................................................................................................. 16-148
Capability Registers........................................................................................... 16-149
Operational Registers......................................................................................... 16-149
Discovery ........................................................................................................... 16-149
Data Structures................................................................................................... 16-150
Operational Model ............................................................................................. 16-150
Priming Receive Endpoints ........................................................................... 16-135
Interrupt/Bulk Endpoint Bus Response Matrix ............................................. 16-137
Setup Phase.................................................................................................... 16-138
Data Phase ..................................................................................................... 16-138
Status Phase ................................................................................................... 16-139
Control Endpoint Bus Response Matrix ........................................................ 16-139
Isochronous Pipe Synchronization ................................................................ 16-141
Isochronous Endpoint Bus Response Matrix................................................. 16-142
Microframe Pipeline ...................................................................................... 16-150
Split State Machines ...................................................................................... 16-151
Asynchronous Transaction Scheduling and Buffer Management ................. 16-151
Periodic Transaction Scheduling and Buffer Management ........................... 16-151
Multiple Transaction Translators................................................................... 16-152
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