MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 200

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4-34
16–18
20–22
24–26
Bits
15
19
23
27
28
29
30
31
SWHR
SWRS
CSHR
BMRS
Name
JSRS
HRS
BSF
—
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Boot sequencer fail. If set, indicates that the I
configuration words. Cleared by writing a 1 to it (writing zero has no effect).
Reserved, should be cleared.
Software hard reset. If set, indicates a software hard reset. SWHR is cleared by writing a 1 to it (writing
zero has no effect).
Reserved, should be cleared.
JTAG soft reset status. Set when the JTAG reset request is set and remains set until software clears it.
JSRS is cleared by writing a 1 to it (writing zero has no effect).
0 No JTAG reset event.
1
Reserved, should be cleared.
the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by writing a 1
to it (writing zero has no effect).
0 No enabled check stop reset event.
1 Enabled check stop reset event.
Software watchdog reset status. When a software watchdog expire event (which causes a reset) is
detected, SWRS is set and remains that way until the software clears it. SWRS is cleared by writing a
1 to it (writing zero has no effect).
0 No software watchdog reset event.
1 Software watchdog reset event.
Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected, BMRS
is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it (writing zero
has no effect).
0 No bus monitor reset event.
1 Bus monitor reset event.
Reserved
set until software clears it. HRS is cleared by writing a 1 (writing zero has no effect).
0 No hard reset event.
1 Hard reset event.
Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled by
Hard reset status. When an external or internal hard reset event is detected, HRS is set and remains
Table 4-28. Reset Status Register Field Descriptions (continued)
JTAG reset event.
Description
2
C boot sequencer has failed while loading the reset
Freescale Semiconductor