MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1182

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Revision History
1.1, 1-6
1.2.6, 1-14
2.3, 2-5
3.1, 3-1
3.1, 3-20
4.3.1.1, 4-10
4.3.1.3, 4-11
4.3.2, 14-13
4.3.3.3.2, 4-27
4.4.3, 4-31
4.4.5, 4-33
4.4.7, 4-34
4.5.2.3, 4-42
4.5.2.3, 4-41
5.3.2.5, 5-21
5.3.2.6, 5-25
5.3.2.8, 5-26
A-24
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Replaced ‘Supports wake-up from Ethernet Magic Packet, USB, GPIO, and PCI
(PME input as host),’ with the following:
Supports wake-up from Ethernet Magic Packet, USB, GPIO, PCI (PME input as
host), timer, and external interrupts
Removed Section 1.2.6, “Serial ATA (SATA) Controller.”
In Table 2-2, changed the reset value of SWSRR from 0x0000_0000 to 0x0000,
as it is a 16-bit register.
Throughout book—added signals: USB_PHY_PWR, USB_PHY_GND,
USB_VDDA, USB_VSSA, USB_PLL_PWR1, USB_PLL_PWR3,
USB_PLL_GND0, USB_PLL_GND1, USB_VSSA_BIAS, and
USB_VDDA_BIAS.
Removed signals: SD_PLL_TPA_ANA and SD_PLL_TPD.
Removed Table 3-3, because of inconsistencies between MPC8313 hardware
specification document and the reference manual.
In Table 4-5, for offset 0100, changed PCI frequency range from 25–66.666 MHz
to 24–66.666 MHz.
In Table 4-6, modified the description for CFG_CLKIN_DIV.
In Table 4-8, added more description to DDRCM bit.
Table 4-25, for bits 1, 3, 12–15, and 20–27, removed ‘Reserved, should be
cleared,’ and added ‘Reserved.’ Also reformatted the table.
Removed overbars for the signal CFG_CLKIN_DIV.
Modified Ethernet clocking description.
Deleted Figure 4-8 and replaced it with Table 4-8, “System Clock Frequencies.”
Table 4-37, changed the description for [4:5], [12:14], and [16:31] by removing
‘should be cleared.’
Table 4-38, in ENCCM description, replaced ‘Encryption core clock mode,’ with
‘Encryption core and I2C1 clock mode.’
In Table 5-27, replaced incomplete set of 1588 signals (TSEC_TMR_CLK,
TSEC_TMR_CLK_OUT, TSEC_TMR_TRIG_IN, TSEC_TMR_TRIG_OUT,
TSEC_TMR_PULSE_OUT1, TSEC_TMR_PULSE_OUT2), with the complete
set ( TSEC_1588_CLK, TSEC_1588_GCLK, TSEC_1588_TRIG1,
TSEC_1588_TRIG2, TSEC_1588_PP1, TSEC_1588_PP2, TSEC_1588_PP3,
TSEC_1588_ALARM1, TSEC_1588_ALARM2).
In Table 5-29 added footnote for bit SICRH[30]:
If RCWH[ETSEC1M] is RGMII/RTBI then the reset value is 1, otherwise it is 0.
In Table 5-30, rewrote DSO_EN and Q_DRN description:
DDR driver software override is disable when DSO_EN is 0 and is enable when
DSO_EN is 1. Drain queue before sleep is disable when Q_DRN is 0 and enable
when Q_DRN is 1.
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