MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 943

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
31–16
Bits
15
14
13
12
11
10
9
8
7
Name
ULPII
HCH
RCL
SRI
SLI
AS
PS
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared.
Asynchronous schedule status. Reports the current real status of the asynchronous schedule. The
USB DR controller is not required to immediately disable or enable the asynchronous schedule when
software transitions USBCMD[ASE]. When this bit and USBCMD[ASE] have the same value, the
asynchronous schedule is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
Periodic schedule status. Reports the current real status of the periodic schedule. The USB DR
controller is not required to immediately disable or enable the periodic schedule when software
transitions USBCMD[PSE]. When this bit and USBCMD[PSE] have the same value, the periodic
schedule
is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
Reclamation. Used to detect an empty asynchronous schedule. Only used by the host mode.
0 Non-empty asynchronous schedule
1 Empty asynchronous schedule
HC haIted. This bit is a zero whenever USBCMD[RS] is a one. The USB DR controller sets this bit to
one after it has stopped executing because of USBCMD[RS] being cleared, either by software or by
the host controller hardware (for example, internal error). Only used in host mode.
0 Running
1 Halted
Reserved, should be cleared.
ULPI interrupt. An event completion to the viewport register sets this bit. If the ULPI enables the
USBINTR[ULPIE] to be set, the USB interrupt (UI) will occur.
Reserved, should be cleared.
DCSuspend. This is a non-EHCI bit. When a device controller enters a suspend state from an active
state, this bit is set. The device controller clears the bit upon exiting from a suspend state. Only used
by the device controller.
0 Active
1 Suspended
Host mode:
Device mode:
Software writes a 1 to this bit to clear it.
• This is a non-EHCI status bit. In host mode, this bit will be set every 125 us, provided the PHY clock
• SOF received. When the USB DR controller detects a Start Of (Micro)Frame, this bit will be set.
is present and running (for example, the port is NOT suspended), and can be used by the host
controller driver as a time base.
When a SOF is extremely late, the DR controller will automatically set this bit to indicate that an
SOF was expected. Therefore, this bit will be set roughly every 1 msec in device FS mode and
every 125 msec in HS mode and will be synchronized to the actual SOF that is received. Because
the controller is initialized to FS before connect, this bit will be set at an interval of 1 msec during
the prelude to the connect and chirp.
Table 16-11. USBSTS Register Field Descriptions
Description
Universal Serial Bus Interface
16-15