MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 963

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.3.2.17 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
This register is not defined in the EHCI specification. This register contains the endpoint setup status. It is
only used in device mode.
16.3.2.18 Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to initialize endpoints. It is only
used in device mode.
Freescale Semiconductor
Offset 0x2_31B0
Reset
Offset 0x2_31AC
Reset
31–19
18–16 PETB Prime endpoint transmit buffer. For each endpoint a corresponding bit is used to request that a buffer prepared
31–3
Bits
Bits
2–0
W
W
R
R
31
31
Name
ENDPTSETUP
—
Name
STAT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
Reserved, should be cleared.
for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one
to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB[2] (bit 18 of the
register) corresponds to endpoint 2.
Note that these bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
Reserved, should be cleared.
Setup endpoint status. For every setup transaction that is received, a corresponding bit in this
register is set. Software must clear or acknowledge the setup transfer by writing a one to a respective
bit after it has read the setup data from queue head. The response to a setup packet as in the order
of operations and total response time is crucial to limit bus time outs while the setup lockout
mechanism is engaged.
This register is only used in device mode.
Table 16-26. ENDPTSETUPSTAT Register Field Descriptions
—
Figure 16-23. Endpoint Setup Status (ENDPTSETUPSTAT)
Table 16-27. ENDPTPRIME Register Field Descriptions
Figure 16-24. Endpoint Initialization (ENDPTPRIME)
19 18
PETB
—
16 15
All zeros
All zeros
Description
Description
—
Universal Serial Bus Interface
3
Access: Read/Write
Access: Read/Write
ENDPTSETUP
2
3
STAT
2
PERB
16-35
0
0