MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 699

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.5.1.2
The crypto-channel pointer status register (CCPSR) contains status fields and counters that provide the
user with status information regarding the channel’s actual processing of a given descriptor.
Table 14-32
Freescale Semiconductor
12–15
16–19
20–23
24–31
32–37
8–11
Bits
0–2
3–7
Reset
Reset
Field
Field
Addr
Addr
FF_COUNTER Fetch FIFO counter. This 5-bit counter indicates how many fetch pointers are currently stored in the
R/W
R/W
CHN_STATE
G_STATE
S_STATE
Names
describes the CCPSR fields.
Crypto-Channel Pointer Status Register (CCPSR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
—
—
32 - 37
—
0–2
—
Figure 14-37. Crypto-Channel Pointer Status Register (CCPSR)
Reserved
FIFO.
Reserved
Gather state machine state. This field reflects the state of the channel Gather control state machine.
The value of this field indicates which stage the channel is while performing gather function.
Table 14-33
G_State is documented for information only. The User will not typically care about the gather state
machine.
Reserved.
Scatter state machine state. This field reflects the state of the channel Scatter control state machine.
The value of this field indicates which stage the channel is while performing scatter function.
Table 14-33
S_State is documented for information only. The User will not typically care about the scatter state
machine.
State. State of the channel state machine. This field reflects the state of the channel control state
machine. The value of this field indicates exactly which stage the channel is in the sequence of
fetching and processing data descriptors.
the STATE field.
Note: CHN_State is documented for information only. The User will not typically care about the
Reserved, set to zero
MI MO PR
38
channel state machine.
FF_COUNTER
39
Table 14-32. CCPSR Field Descriptions
shows the meaning of all possible values of the G_STATE field.
shows the meaning of all possible values of the S_STATE field.
3–7
40
SR
41
PG
42
8–11
—
Channel_1 0x01110
Channel_1 0x01114
SG PRD SRD PD
43
0x0_0000
0x0_0007
G_STATE
44
R
R
12–15
Table 14-34
Description
45
46
16–19
—
shows the meaning of all possible values of
SD
47
S_STATE
20–23
48–59
Error
CHN_STATE
Security Engine (SEC) 2.2
PAIR_PTR
24–31
60–63
14-57