MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 575

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

12.3.8.8
DMAGSR provides faster access to the status bits by combining the status bits of all of the DMA channels
into one register. Each byte of this register provides the value of bits 7–0 of a channel’s DMA status
register. These bits are cleared by writing to the individual DMA status registers.
DMAGSR fields.
12.4
12.4.1
An embedded processor is often part of a larger system containing many processors and distributed
memory. These processors tend to work on tasks independent of the host and other peripheral processors
in the system. Because of the independent nature of the tasks, it is necessary to provide a communication
mechanism between the peripheral processors and the rest of the system. One such method is the use of
messages. This block provides a messaging unit to further facilitate communications between host and
peripheral. The message unit uses generic messages and doorbell registers.
12.4.1.1
There are two 32-bit inbound message registers (IMR0–IMR1) and two 32-bit outbound message registers
(OMR0–OMR1). IMR0 and IMR1 allow a remote host or PCI master to write a 32-bit value that, in turn,
causes an interrupt request to the on-chip interrupt controller that drives an interrupt line to the local
processor. OMR0 and OMR1 allow the local processor to write an outbound message which, in turn,
causes the outbound interrupt signal PCI_INTA to assert.
The interrupt to the local processor is cleared by writing 1 to the appropriate IMISR bit. The interrupt to
PCI (PCI_INTA) is cleared by writing 1 to the appropriate OMISR bit.
Freescale Semiconductor
Offset 0x2A8
Reset
Bits
2–1
0
W
R
31
Name
EOTD
Functional Description
—
Channel 0 Status
Message Unit
DMA General Status Register (DMAGSR)
Messaging Registers (IMR0–IMR1, OMR0–OMR1)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
End-of-transfer descriptor.
0 This descriptor contains a link to another descriptor.
1 This descriptor is the last to be executed.
Table 12-16. DMANDAR n Field Descriptions (continued)
Figure 12-17. DMA General Status Register (DMAGSR)
24 23
Channel 1 Status
All zeros
16 15
Descriptions
Channel 2 Status
8
Figure 12-17
7
Access: User Read/Write
Channel 3 Status
DMA/Messaging Unit
shows the
12-15
0