MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 691

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.3.9
There are seven 64-bit context data registers that allow the host to read/write the contents of the context
used to process the message. The context must be written prior to the key data. If the context registers are
written during message processing, a context error will be generated. All context registers are cleared
when a hard/soft reset or initialization is performed.
The context registers must be read when changing context and restored to their original values to resume
processing an interrupted message (CBC, CTR, and CCM modes). For CTR and CCM mode, all seven
64-bit context registers must be read to retrieve context, and all seven must be written back to restore
context. Effectively, the user must read the four empty ‘place holder’ context registers in addition to the
three context registers holding the Counter and Counter Modulus Exponent when in CTR mode. The
contents of the ‘empty’ context registers need not be preserved, but when restoring the CTR mode context,
the ‘empty’ registers must be filled with 32 bytes of zeros before writing the saved Counter and Counter
Modulus Exponent.
Context should be loaded with the lower bytes in the lowest 64-bit context register. The context registers
are summarized in
1
2
3
Freescale Semiconductor
Must be written at the start of a new message.
Must be written at start of new CCM decryption.
Header size/MAC size is only used if AES-CCM processing is suspended and resumed.
Cipher Mode
Reset
Field
Addr
R/W
CCM
CBC
ECB
CTR
SRT
AESU Context Registers
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
IV1
Figure
—
—
IV
1
1
1
Counter
/ MAC Tag
Figure 14-33. AESU End-of-Message Register (AESUEMR)
14-34.
1
IV2
—
—
2
1
Figure 14-34. AESU Context Registers
Counter Modulus
Exponent (M)
Encrypted MAC
MAC/Encrypted Counter
—
—
—
3
Context Register (64 bits each)
AESU End of Message
AESU 0x3_4050
1
2
/Decrypted
W
0
—
—
—
—
4
—
—
—
5
Counter
Counter
1
1
—
—
—
6
Security Engine (SEC) 2.2
Exponent
Counter Modulus
Counter Modulus
size/MAC size
Exponent
—
—
—
7
1
63
/header
14-49
1
3