MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 428

no-image

MPC8313ZQADDC

Manufacturer Part Number
MPC8313ZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO ENC
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313ZQADDC

Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8313ZQADDC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
DDR Memory Controller
If a transaction request is issued to the DDR memory controller and the address does not lie within any of
the programmed address ranges for an enabled chip select, a memory select error is flagged.
Using a memory-polling algorithm at power-on reset or by querying the JEDEC serial presence detect
capability of memory modules, system firmware uses the memory-boundary registers to configure the
DDR memory controller to map the size of each bank in memory. The memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank starting
and ending addresses. The memory banks are not required to be mapped to a contiguous address space.
9.5.2
Table 9-27
address presented at the memory controller signals MA[14:0] use MA[14] as the msb and MA[0] as the
lsb. Also, MA[10] is used as the auto-precharge bit in DDR1/DDR2 modes for reads and writes, so the
column address can never use MA[10].
9-34
1
SDRAM Device
SDRAM Device
This configuration is not supported in 16-bit bus mode.
256 Mbits
256 Mbits
512 Mbits
512 Mbits
1 Gbits
2 Gbits
2 Gbits
1 Gbits
1 Gbits
2 Gbits
2 Gbits
4 Gbits
4 Gbits
and
DDR SDRAM Address Multiplexing
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 9-28
Table 9-25. Supported DDR1 SDRAM Device Configurations (continued)
Device Configuration
Device Configuration
Table 9-26. Supported DDR2 SDRAM Device Configurations
128 Mbits x 16
256 Mbits x 16
128Mbits x 16
64 Mbits x 16
256 Mbits x 8
16 Mbits x 16
32 Mbits x 16
128 Mbits x 8
64 Mbits x 16
512 Mbits x 8
256Mbits x 8
32 Mbits x 8
64 Mbits x 8
show the address bit encodings for each DDR SDRAM configuration. The
Row x Column x
Row x Column x
Sub-bank Bits
Sub-bank Bits
14 x 10 x 2
15 x 11 x 2
15 x 10 x 2
13 x 10 x 2
14 x 10 x 2
13 x 10 x 2
14 x 10 x 3
13 x 10 x 3
15 x 10 x 3
14 x 10 x 3
15 x 11 x 3
15 x 10 x 3
13 x 9 x 2
32-Bit Bank Size
32-Bit Bank Size
256 Mbytes
512 Mbytes
128 Mbytes
256 Mbytes
128 Mbytes
512 Mbytes
256 Mbytes
512 Mbytes
64 Mbytes
1 Gbytes
1 Gbyte
2 Gbyte
1 Gbyte
Two Banks of Memory
Two Banks of Memory
512 Mbytes
256 Mbytes
128 Mbytes
512 Mbytes
256 Mbytes
512 Mbytes
Freescale Semiconductor
2 Gbytes
2 Gbytes
1 Gbytes
4 Gbytes
2 Gbytes
1 Gbyte
1 Gbyte

Related parts for MPC8313ZQADDC