MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 726

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.4.1
Below is a description of the eTSEC interface signals. For RGMII mode details please refer to the
Hewlett-Packard reduced gigabit media-independent interface (RGMII) specification version 1.2a, dated
9/22/2000. RMII mode details follow the RMII Consortium Specification, dated 3/20/1998. All other
modes follow the IEEE 802.3 standard, 2000 Edition. Input signals not used are internally disabled. Except
for TSECn_GTX_CLK, output signals not used are driven low.
15-8
TSEC n _GTX_CLK
Signal Name
TSEC n _CRS
TSEC n _COL
RXA/RXA
TXA/TXA
Signal
Detailed Signal Descriptions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 15-1. eTSEC n Network Interface Signal Properties (continued)
Serial transmitter, lane A, positive data (and negative data, complement)
Serial receiver, lane A, positive data (and negative data, complement)
I/O
O
I
I
Table 15-2. eTSEC Signals—Detailed Signal Descriptions
Collision input. The behavior of this signal is not specified while in full-duplex mode.
Carrier sense input. In RTBI mode, this signal is used as SDET (signal detect). In RTBI mode
SDET is tied high internally.
This signal is not used in the following modes:
Gigabit transmit clock. This signal is an output from the eTSEC into the PHY. TSEC n _GTX_CLK
is a 125-MHz clock that provides a timing reference for TX_EN, TXD, and TX_ER in the following
modes:
In RGMII mode, TSEC n _GTX_CLK becomes the transmit clock and provides timing reference
during 1000Base-T (125 MHz), 100Base-T (25 MHz) and 10Base-T (2.5 MHz) transmissions.
This signal feeds back the uninverted transmit clock in MII mode, but feeds back an inverted
transmit clock in RTBI or RGMII modes.
This signal is driven low unless transmission is enabled.
Meaning
Meaning
• RMII
• RGMII
• RTBI
Timing Asserted/Negated—This signal is not required to transition synchronously with
Timing Asserted/Negated—This signal is not required to transition synchronously with
State
State
Asserted/Negated—In MII mode, this signal is asserted upon detection of a collision,
This signal is not used in the following modes:
Asserted/Negated—In MII mode, TSEC n _CRS is asserted while the transmit or
• RMII
• RTBI
• RGMII
and must remain asserted while the collision persists.
TSEC n _TX_CLK or TSEC n _RX_CLK.
receive medium is not idle. In the event of a collision, TSEC n _CRS must remain
asserted for the duration of the collision.
TSEC n _TX_CLK or TSEC n _RX_CLK.
Function
Description
Freescale Semiconductor
Reset
State
—
—