MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 725

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
TSEC_1588_ALARM1 1588—Timer alarm 1
TSEC_1588_ALARM2 1588—Timer alarm 2
TSEC_1588_TRIG1
TSEC_1588_TRIG2
TSEC_1588_GCLK
TSEC_1588_CLK
TSEC_1588_PP1
TSEC_1588_PP2
TSEC_1588_PP3
TSEC n _TXD[3:0]
TSEC n _TX_CLK
TSEC n _RX_ER
TSEC n _TX_ER
TSEC n _TX_EN
SD_REF_CLK,
SD_REF_CLK
Signal Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 15-1. eTSEC n Network Interface Signal Properties (continued)
MII, RMII—Receive error, input
RGMII, RTBI—Unused
MII—transmit clock, input
RMII—reference transmit and receive clock, input
RGMII, RTBI—unused
MII—Transmit data bits 3:0, output
RGMII (TX_CLK rising)—Transmit data bits 3:0, output
RGMII (TX_CLK falling)—Transmit data bits 7:4, output
RTBI (TX_CLK rising)—TCG bits 3:0, output
RTBI (TX_CLK falling)—TCG bits 8:5, output
RMII—TXD[1:0] transmit data bits, output
RMII—TXD[3:2] unused, output driven zero
MII—transmit error, output
RGMII, RTBI, RMII—unused, output driven zero
MII, RMII—Transmit data valid, output
RGMII (TX_CLK rising)—Transmit data enabled, output
RGMII (TX_CLK falling)—Transmit error, output
RTBI (TX_CLK rising)—TCG bit 4, output
RTBI (TX_CLK falling)—TCG bit 9, output
1588—Clock input
External high precision timer reference clock input (chip external input pin).
1588—Clock output
Phase aligned timer clock divider output (chip external output pin).
1588—Trigger in 1
External timer trigger input 1. This is an asynchronous general purpose input (chip external
input pin).
1588—Trigger in 2
External timer trigger input 2. This is an asynchronous general purpose input (chip external
input pin).
1588—Pulse out 1
Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external output pin).
1588—Pulse out 2
Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external output pin).
1588—Pulse out 3
Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external output pin).
Timer current time is equal to or greater than alarm time comparator register. User
reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external
output pin).
Timer current time is equal to or greater than alarm time comparator register. User
reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external
output pin).
SerDes PLL reference clock (and complement)
Function
Enhanced Three-Speed Ethernet Controllers
Reset
State
0000
—
—
—
—
—
—
0
0
0
0
0
0
0
0
15-7