MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1066

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.8.3.5
16.8.3.5.1
All requests to a control endpoint begin with a setup phase followed by an optional data phase and a
required status phase. The USB_DR will always accept the setup phase unless the setup lockout is
engaged.
The setup lockout will engage so that future setup packets are ignored. Lockout of setup packets ensures
that while software is reading the setup packet stored in the queue head, that data is not written as it is being
read potentially causing an invalid setup packet.
The setup lockout mechanism can be disabled and a tripwire type semaphore will ensure that the setup
packet payload is extracted from the queue head without being corrupted be an incoming setup packet.
This is the preferred behavior because ignoring repeated setup packets due to long software interrupt
latency would be a compliance issue.
Setup Packet Handling
16.8.3.5.2
Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime
the transfer.
After priming the packet, the DCD must verify a new setup packet has not been received by reading the
ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete
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Disable Setup Lockout by writing ‘1’ to Setup Lockout Mode (SLOM) in USBMODE (once at
initialization). Setup lockout is not necessary when using the tripwire as described below.
After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet
was received on a particular pipe:
— Write ‘1’ to clear corresponding bit ENDPTSETUPSTAT.
— Write ‘1’ to Setup Tripwire (SUTW) in USBCMD register.
— Duplicate contents of dQH.SetupBuffer into local software byte array.
— Read Setup TripWire (SUTW) in USBCMD register. (if set—continue; if cleared—goto 2)
— Write ‘0’ to clear Setup Tripwire (SUTW) in USBCMD register.
— Process setup packet using local software byte array copy and execute status/handshake phases.
Control Endpoint Operation Model
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Setup Phase
Leaving the Setup Lockout Mode as ‘0’ will result in a potential compliance
issue.
After receiving a new setup packet the status and/or handshake phases may
still be pending from a previous control sequence. These should be flushed
and de-allocated before linking a new status and/or handshake dTD for the
most recent setup packet.
Data Phase
NOTE
NOTE
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