MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 824

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.48 Receive Filer Rejected Packet Counter (RREJ)
Figure 15-99
Table 15-67
15.5.3.7
This section provides detailed descriptions of the registers used for hash functions. All of the registers are
32 bits wide. The DA field of every received frame is processed through a 32-bit CRC generator (CRC-32
polynomial), and the 8 or 9 most significant bits of the CRC are mapped to a hash table entry. The user
can enable a hash entry by setting its bit. A hash entry usually represents a set of addresses. A hash table
hit occurs if the DA CRC result points to an enabled hash entry. Software may need to further filter the
address in order to eliminate false-positive hits in the hash table.
If RCTRL[GHTX] = 0, the 8 most significant bits of the CRC are used as the hash table index. In this case,
registers IGADDR0–IGADDR7 comprise a 256-entry hash table exclusively for individual (unicast)
address matching, while registers GADDR0–GADDR7 comprise a 256-entry hash table for group
(multicast) address matching. If RCTRL[GHTX] = 1, the group hash table is extended to all 512 entries,
and the 9 most significant bits of the CRC are used as the hash table index. In this case, registers
IGADDR0–IGADDR7 hold hash table entries 0–255 for group addresses, while registers
GADDR0–GADDR7 hold entries 256–511 of the extended group hash table.
See
15-106
10–31
Bits
0–9
Offset eTSEC1:0x2_4740; eTSEC2:0x2_5740
Reset
Section 15.6.2.7.2, “Hash Table Algorithm,”
W
R
Name
RREJ
0
—
describes the fields of the RREJ register.
Hash Function Registers
describes the definition for the RREJ register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Receive filer rejected packet counter. Increments for each frame with valid CRC received, but rejected by
the receive queue filer—either due to a matching rule that asserted the REJ flag or due to filing to a RxBD
ring that was not enabled (see IEVENT[FIQ] error).
Figure 15-99. Receive Filer Rejected Packet Counter Register Definition
Bits
30
31
—
Table 15-102. CAM2 Field Descriptions (continued)
M2TDP
Name
—
Table 15-103. RREJ Field Descriptions
9
Reserved
Mask register 2 TDRP counter carry bit mask
10
for more information on the hash algorithm.
All zeros
Description
Description
RREJ
Freescale Semiconductor
Access: Read/Write
31