MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 437

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.5.6
To reduce loading, registered DRAM modules latch the DDR SDRAM control signals internally before
using them to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay on the
DRAM modules’ control bus by delaying the data and data mask writes (on SDRAM buses) by an extra
SDRAM clock cycle.
Figure 9-28
9.5.7
The DDR memory controller facilitates system design flexibility by providing a write timing adjustment
parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and DQS. The DDR
SDRAM specification requires DQS be received no sooner than 75% of an SDRAM clock period—and
no later than 125% of a clock period—from the capturing clock edge of the command/address at the
SDRAM. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and
data from the first clock edge occurring one SDRAM clock cycle after the command is launched. The
delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0.
Freescale Semiconductor
DDR SDRAM Registered DIMM Mode
DDR SDRAM Write Timing Adjustments
SDRAM Clock
shows the registered DDR SDRAM DIMM single-beat write timing.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Application system board must assert the reset signal on DDR memory
devices until software is able to program the DDR memory controller
configuration registers, and must deassert the reset signal on DDR memory
devices before DDR_SDRAM_CFG[MEM_EN] is set. This ensures that
the DDR memory devices are held in reset until a stable clock is provided
and, further, that a stable clock is provided before memory devices are
released from reset.
MDM[0:3]
MDQS
MRAS
MCAS
MDQ n
MWE
MCS
MA n
Figure 9-28. Registered DDR SDRAM DIMM Burst Write Timing
ROW
0
1
ACTTORW
2
3
COL
4
NOTE
5
COL
D0
6
D1 D2 D3
7
00
D0
8
D1 D2
9
D3
10
11
DDR Memory Controller
12
9-43